Process Control Technique to Dramatically Reduce Voids in Phosphorus-Doped Poly-Silicon for Trench Field-Plate MOSFETs

Silicon power MOSFETs have been used for a wide variety of electronic devices in many application fields. In order to obtain high breakdown voltage and low on-resistance, trench field-plate (FP) MOSFETs have been continuously developed in recent years. It is necessary to design deep trench and thick field-plate oxide for higher breakdown voltage FP-MOSFETs [1]–[6]. In state-of-the-art FP-MOSFETs, as shown in Fig. 1, high cell density design has been developed for the purpose of getting low on-resistance. Fundamentally, it needs to shrink cell pitch, which consists of trench width and mesa width. Forming vertical trench is one method to realize narrow cell pitch. Voids are, however, generated in source field-plate polysilicon or gate poly-silicon in general [7]. If voids are gathered widely at the bottom of the source field-plate polysilicon (Fig. 1(a)), the effect of field-plate such as high breakdown voltage and good device characteristics cannot be obtained properly. Furthermore, if voids are formed at the bottom edge of the gate poly-silicon (Fig. 1(b)), effective gate bottom edge is underlapped with p-base. Thus, it is difficult to form the channel inversion layer at gate oxide interface. As a result, the on-resistance becomes increased. Therefore, suppressing void generation is one of the most significant process controls for trench FP-MOSFETs.