{"title":"A new SPICE macro-model for simulation of single electron circuits","authors":"M. Karimian, M. Dousti, M. Pouyan, R. Faez","doi":"10.1109/ICM.2009.5418646","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418646","url":null,"abstract":"In this paper we have proposed a new and more accurate macro-model for simulation of single electron transistors (SETs). Furthermore, this model includes the ability of electron tunneling time calculation. In our proposed model, we have modified the previous models and applied some basic corrections to their formulas. In addition to achievement of more accuracy, we have added a switched capacitor circuit, as a quantizer, to evaluate the time of electron tunneling through the barrier. We used HSPICE for high-speed simulation and observed that our macro-model gives more accurate results than of the other models when compare with SIMON 2.0. This model is completely applicable for calculating the delay time of complicated circuits.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122726767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Aissam Berrahou, Yamina Raji, Mourad Rafi, M. Eleuldj
{"title":"Framework for mixed systems","authors":"Aissam Berrahou, Yamina Raji, Mourad Rafi, M. Eleuldj","doi":"10.1109/ICM.2009.5418616","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418616","url":null,"abstract":"In this paper, we present the F4MS (Framework for Mixed Systems) which is a Computer Aided Design for software and hardware design, simulation and aided execution. Based on components which could be software or/ and hardware, as well as all operational tools. This framework is an extension of the TI4CS framework (Tools Integration for Complex Software), witch deals only with softwares components. In order to design a mixed systems in this framework we use a general model (execution graph), which characterizes the integration phase in the design methodology. This methodology also covers specification and partitioning phases. Finally, to illustrate this work we propose an example of mixed system for the implementation of the VPN solutions.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124770656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jorgiano Vidal, F. de Lamotte, G. Gogniat, J. Diguet, Philippe Soulard
{"title":"IP reuse in an MDA MPSoPC co-design approach","authors":"Jorgiano Vidal, F. de Lamotte, G. Gogniat, J. Diguet, Philippe Soulard","doi":"10.1109/ICM.2009.5418638","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418638","url":null,"abstract":"With the increasing hardware capacity, embedded systems are becoming more and more complex, requiring new design techniques/methods. UML allows higher abstraction level system modeling and MDA techniques allow automatic code generation. In this paper we propose a UML/MDA approach to rapidly model and automatically generate MPSoPC systems. Our approach uses MARTE as extension mechanism in order to allow real-time and platform embedded systems modeling. Our goal is to provide an unique model for MPSoPC co-design, closing the gap between hardware and software modeling. Also, we propose an efficient method for IP (Intellectual Property) reuse allowing automatically platform code generation. Our tests have shown gains in the order of 30% in design time.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123083642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high-performance CMOS charge pump for PLLs","authors":"Jianbing Pan, Yuanfu Zhao, Xin Liang","doi":"10.1109/ICM.2009.5418578","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418578","url":null,"abstract":"In conventional CMOS charge pump circuits, there are some non-ideal effects such as the clock feedthrough, current mismatch and charge sharing which result in a phase offset in phase-locked loop circuits. This paper presents a new charge pump to reduce the jitter. The proposed and conventional charge pumps are simulated and compared. The circuit is implemented using a 0.35µm mix-signal CMOS process. And the simulation result is obtained by SPECTRES.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"12 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121011902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Yadir, M. Benhmida, M. Sidki, E. Assaid, M. Khaidar
{"title":"New method for extracting the model physical parameters of solar cells using explicit analytic solutions of current-voltage equation","authors":"S. Yadir, M. Benhmida, M. Sidki, E. Assaid, M. Khaidar","doi":"10.1109/ICM.2009.5418599","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418599","url":null,"abstract":"In this paper, we present a new method of extracting the model physical parameters of an illuminated solar cell, composed of series and shunt resistance. The method is based on analytical solution of the equation derived from the current-voltage (I-V) characteristics. The equation obtained is expressed in terms of I, V, and the derivative (dI/dV). The model parameters can then be easily determined by numerical fitting. The obtained results show a good agreement with those obtained by the method proposed by Ortiz-Conde et al., and by the five-point method.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. S. Abdellatif, A. E. Rouby, Mohamed B. Abdelhalim, A. Khalil
{"title":"Interconnects parasitic extraction using modified Particle Swarm Optimization","authors":"A. S. Abdellatif, A. E. Rouby, Mohamed B. Abdelhalim, A. Khalil","doi":"10.1109/ICM.2009.5418619","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418619","url":null,"abstract":"Three new Particle Swarm Optimization approaches are proposed. We used these approaches to solve a Curve fitting problem for Parasitic Extraction Macro-modeling application. In the first proposed approach, Wiggling PSO (WPSO); we enforce the particles to vibrate in their motion towards the best position -instead of straight motion- to enlarge the scanning area. The second approach, Incrementally Social PSO (ISPSO); is utilizing a variable weight for the social term (xg-x). This variability enables changing the social relationship between the particles from highly repulsive to highly attractive. Finally, we proposed a new Control inspired approach, PID-PSO, where we dealt with the PSO motion as a process that needs a controller to be optimized. It is quite common to use PSO to tune PID parameters but in this context we used PID to tune PSO motion. The performances of these three proposed approaches were measured on an extensive real data sets and used along with the understanding of the physical problem to offer various explanations of the theoretical aspects of the new algorithms.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"600 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132828976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"GRT model of RTS noise in MOSFETs","authors":"J. Sikula, J. Pavelka, M. Tacano, M. Toita","doi":"10.1109/ICM.2009.5418625","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418625","url":null,"abstract":"Random Telegraph Signal (RTS) noise in submicron MOSFETs showing a capture process, which deviates from the standard Shockley-Read-Hall kinetics, is analyzed using generation-recombination-tunneling model of current modulation in order to explain quadratic dependence of capture rate on current. Proposed model of two-step charge carrier quantum transitions involving secondary trap at the channel and gate oxide interface better represents observed complex switching phenomena in nanoscale devices, as is confirmed by presented experimental results.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134259846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Functional mapping for nanodevice-based architectures","authors":"M. Amadou, S. Le Beux, G. Nicolescu, I. O’Connor","doi":"10.1109/ICM.2009.5418665","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418665","url":null,"abstract":"Recently, technology advancement led to the emergence of nanodevice-based architectures. By exploiting the fine-grain dynamic reconfigurability of these logic cells, nanodevice-based architectures are expected, compared to conventional architectures, to reduce area and cost, and improve performance over a broad range of applications. In order to explore the potential of these architectures, the definition of new CAD tools is required. This paper discusses the challenges for system-level exploration for nanodevice-based architectures and proposes an approach enabling automatic application partitioning and mapping for these architectures.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131520836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-voltage DC/DC converter for high-efficiency power recovery in implantable devices","authors":"F. Mounaim, M. Sawan","doi":"10.1109/ICM.2009.5418643","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418643","url":null,"abstract":"Implantable biomedical devices such as sensors and neurostimulators require a near-field inductive link to transmit power wirelessly. However, the near-field induced voltage is usually much larger than the compliance of low-voltage integrated circuit technologies. Thus most integrated power recovery approaches limit the induced signal to low-voltages with inefficient shunt regulation, or voltage clipping. We propose using a high-voltage (HV) CMOS technology to fully integrate the inductive power recovery front-end while adopting a step-down approach where the induced signal is limited to a much higher voltage (20 V). We previously reported a first IC that includes a HV rectifier and a HV regulator, which provide up to 12 V regulated DC supply from a 20 V maximum AC input. In this paper, we report the design of a second HV custom IC that completes the front-end by integrating an adjustable step-down switched capacitor DC/DC converter (1:3, 1:2 or 2:3 ratio). The IC has been submitted for fabrication in DALSA-C08E technology and the total silicon area including pads is 9mm2. Post-layout simulation results show that the DC/DC converter achieves more than 90 % power efficiency while providing about 3.9 V output with 12 V input, 1 mA load, 1:3 conversion ratio, and 50 kHz switching frequency.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123339487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"WiMAX integrated PC for emerging markets","authors":"P. Modali, Prashanth Adiraju, A. Biswas","doi":"10.1109/ICM.2009.5418673","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418673","url":null,"abstract":"India is making rapid progress in GDP growth resulting in the growth of numbers and income of the middle class. However, PC and broadband penetration are approximately 3% and 2% respectively. Desirability & affordability are becoming the most influencing consumption factors for the growing middle class. Bringing technology to large and upcoming middle class consumers requires localization efforts that define \"value for money\" in the local context. Although the current numbers are small, India is seeing a rapid growth in broadband subscribers. There is national consensus on the economic impact of broadband today. The objective of this project is two-fold. First is to improve the desirability of PC by integrating Internet connectivity. Second objective is to improve the affordability of the PC through integration of connectivity, chassis and antenna optimizations. Connected and affordable WiMAX PC initiative could help bridge the gap in the \"digital divide\" by providing means and access to information and knowledge in India.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124620773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}