2009 International Conference on Microelectronics - ICM最新文献

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An 8Hz, 0.1µW, 110+ dBs Sinh CMOS Bessel filter for ECG signals 8Hz, 0.1µW, 110+ db Sinh CMOS贝塞尔滤波器用于心电信号
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418668
E. Kardoulaki, K. Glaros, A. Katsiamis, E. Drakakis
{"title":"An 8Hz, 0.1µW, 110+ dBs Sinh CMOS Bessel filter for ECG signals","authors":"E. Kardoulaki, K. Glaros, A. Katsiamis, E. Drakakis","doi":"10.1109/ICM.2009.5418668","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418668","url":null,"abstract":"Hyperbolic sine (Sinh) CMOS filters are of inherent class-AB nature and offer high dynamic range at half the total capacitance value when compared against their pseudodifferential class-AB log-domain counterparts. This characteristic renders their theoretical and practical study valuable. Only a very limited number of CMOS Sinh filter topologies have been reported in the literature to date mostly due to the considerably increased mathematical complexity associated with their design. This paper presents the transistorlevel synthesis and investigates in detail the performance of a 3rd-order Sinh CMOS 8Hz low-pass filter of Bessel approximation suitable for ECG processing. The filter is based on recent progress made and has been designed in the commercially available 0.35µm AMS process. Its static power consumption amounts to 0.1µW while its dynamic range exceeds 110dBs. The new filter exhibits a flat group delay of less than 1% error up to 6Hz and good variability performance verified by means of Monte Carlo simulations. The suitability of the filter as part of an ECG front-end is confirmed by the processing of artificially generated ECG signals contaminated by various simulated noise sources and fed as signal inputs into the Cadence Design Framework.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115180809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Processing APL properties to generate verification-ready MDG model 处理APL属性以生成可验证的千年发展目标模型
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418635
K. Hussain, O. Mohamed, Sa'ed Abed
{"title":"Processing APL properties to generate verification-ready MDG model","authors":"K. Hussain, O. Mohamed, Sa'ed Abed","doi":"10.1109/ICM.2009.5418635","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418635","url":null,"abstract":"Multiway Decision Graphs (MDGs) are special decision diagrams that subsume Binary Decision Diagrams (BDDs) and extend them by a first-order formulae suitable for model checking of datapath circuits. In this paper we propose a new specification language, Abstract Property Language (APL), for the MDG model-checker. The APL language eradicates the restrictions present in the existing LMDG specification language and introduces new operators to improve expressiveness. The paper also presents the design of a front-end translator that accepts specification in APL and builds composite MDG model with the specification directly embedded into its MDG-HDL representation. Finally, some experimental results are presented to show the performance of the APL-Tool and the analysis of the generated code executed on benchmark properties.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124357010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel framework of Optimizing modular computing architecture for multi objective VLSI designs 一种面向多目标超大规模集成电路设计的模块化计算结构优化新框架
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418618
Zhipeng Zeng, R. Sedaghat, A. Sengupta
{"title":"A novel framework of Optimizing modular computing architecture for multi objective VLSI designs","authors":"Zhipeng Zeng, R. Sedaghat, A. Sengupta","doi":"10.1109/ICM.2009.5418618","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418618","url":null,"abstract":"For the past few years modular design has become the de facto standard for the development of complex VLSI systems. Most of these modular VLSI system designs are generally multi objective in nature with the requisite to tradeoff between many contradictory parameters like speed, power consumed, cost and hardware area. They are heavily used in low end ASIC's which demand low power consumption and cost with acceptable performance and in high end ASIC's with high performance requirement. This paper presents a novel framework for the optimization of computing architecture based on hierarchy factor method. The determination of this hierarchy factor enables the designer to arrange the various resources of the system in the form of an architecture tree based on the application and the user specifications. The resulting structure would act as a pathway for obtaining the optimal architecture design option for multi objective optimization of the computing architecture used in many VLSI designs. The framework for optimization of computing architecture shown in this paper has been deduced and proved mathematically. The proposed method is capable to determine the most influential resource for a certain performance parameter in the whole system which is deduced by considering the mathematical model of the performance metric. The representation of our approach in the form of architecture tree allows easy automation of the process, useful for many multi objective optimized VLSI designs.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121287814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
DSP-controlled direct torque control of induction machines based on modulated hysteresis control 基于调制磁滞控制的感应电机直接转矩控制
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418603
Djamila Rekioua, T. Rekioua
{"title":"DSP-controlled direct torque control of induction machines based on modulated hysteresis control","authors":"Djamila Rekioua, T. Rekioua","doi":"10.1109/ICM.2009.5418603","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418603","url":null,"abstract":"The purpose of this paper is to describe a new method for modulated hysteresis direct torque control algorithm for induction motor (IM) to minimize torque ripple and to obtain a constant switching frequency. The design methodology is based on space vector modulation of electrical machines with digital vector control. MATLAB simulations supported with experimental study under C++ are used. -The simulation and experimental results of this proposed algorithm show adequate dynamic to IM, however the research can be extended to include synchronous motor as well. The implementation of the proposed algorithm in microcontroller embedded systems is described. It requires no PI controller in the torque control loop. Results obtained from simulation and experiments confirmed the feasibility of the proposed strategy comparing to the conventional","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128326451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Sigma-delta A/D converter for CMOS image sensors 用于CMOS图像传感器的Sigma-delta A/D转换器
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418577
P. M. Silva, V. Correia, S. Mendez, J. G. Rocha
{"title":"Sigma-delta A/D converter for CMOS image sensors","authors":"P. M. Silva, V. Correia, S. Mendez, J. G. Rocha","doi":"10.1109/ICM.2009.5418577","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418577","url":null,"abstract":"This paper describes the per-pixel readout circuit of an imaging matrix and compares it with other solutions. The per-pixel readout circuit consists in a digital pixel sensor array constituted by a photodiode and a one-bit first-order sigma-delta analog to digital converter for each pixel. The output of each pixel is a digital bit stream, containing information about the intensity of the light that falls into its photodiode. The sigma-delta A/D converters use only ten small size MOSFETs and one capacitor. The comparison between the solution presented here and other solutions show that the circuit complexity is similar but the performance, in terms of signal to noise ratio, is superior.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126502699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Didactic simulation of a metal oxide semiconductor structure 金属氧化物半导体结构的教学模拟
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418626
H. Magrez, K. Kassmi, A. Ziyyat
{"title":"Didactic simulation of a metal oxide semiconductor structure","authors":"H. Magrez, K. Kassmi, A. Ziyyat","doi":"10.1109/ICM.2009.5418626","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418626","url":null,"abstract":"In this paper, we present an interactive simulation of a Metal-Oxide-Semiconductor structure, based on a qualitative approach. The code is written in ActionScript / Flash to enjoy all the benefits of this technology in the multimedia field. In addition, our simulation combines theoretical and practical concepts on the same graphical interface: it shows the impact of physical and electrical parameters on the behavior of a MOS structure or a transistor TMOS. Moreover, it provides the physical reasons of the parameters influence that can serve to evaluate the relevance of approximations commonly used. This simulation is applied in engineering education.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117240007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An FPGA implementation of AES with fault analysis countermeasures 带故障分析对策的AES的FPGA实现
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418647
A. A. Kamal, A. Youssef
{"title":"An FPGA implementation of AES with fault analysis countermeasures","authors":"A. A. Kamal, A. Youssef","doi":"10.1109/ICM.2009.5418647","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418647","url":null,"abstract":"Fault analysis attacks are powerful cryptanalytic tools that are applicable to many types of cryptosystems. Inducing multiple transient faults and observing the output of the faulty cryptographic device may allow the attacker to collect sufficient information for extracting secret keys and even using the device after breaking the cipher. In this paper, we investigate several options for fault analysis resistant FPGA implementations of the Advanced Encryption Standard (AES), which has become the default choice for various security services in many applications since its adaption as a new encryption standard by NIST. In particular, we compare the throughput and area overheads associated with parity based error detection and (algorithm level, round level and operation level) redundancy based countermeasures. Our comparison also include implementations that already employ some additional countermeasures against power analysis attacks.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132006390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Robust NTF design for continuous time Sigma-Delta modulators 连续时间σ - δ调制器的鲁棒NTF设计
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418581
M. Mirzaei, H. Shamsi
{"title":"Robust NTF design for continuous time Sigma-Delta modulators","authors":"M. Mirzaei, H. Shamsi","doi":"10.1109/ICM.2009.5418581","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418581","url":null,"abstract":"In this paper, a novel empirical-analytical study is performed on the design of low power and robust continuous time Sigma-Delta modulators. The proposed method makes the modulators more stable against the excess loop delay of the feedback loop. Besides, it enforces easy constraints on op-amps of the modulator so that we can realize the op-amps with a unity gain bandwidth identical to the sampling frequency of the modulator. In order to design a more stable Noise Transfer Function (NTF), this method employs both the phase margin (PM) and gain margin (GM) stability criteria.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124893424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PSpice modelling nonlinearity effects on ultrasonic waves PSpice模拟超声波的非线性效应
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418582
N. Aouzale, A. Chitnalah, H. Jakjoud
{"title":"PSpice modelling nonlinearity effects on ultrasonic waves","authors":"N. Aouzale, A. Chitnalah, H. Jakjoud","doi":"10.1109/ICM.2009.5418582","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418582","url":null,"abstract":"Nonlinearity is one of the phenomena that affect the ultrasonic wave during its propagation in a given medium. In the time domain the nonlinearity is seen as a variation of the phase velocity which leads to a distortion of the wave form that corresponds in the frequency domain to energy transfer from the fundamental frequency to the harmonic and among the harmonic themselves. Our previous work was axed on the modelling with the simulation tool PSpice of the absorption and the diffraction effects on the wave propagation. The aim of this paper is to introduce the PSpice implementation of the computational model of the nonlinear ultrasound propagation. We study first the plane wave distortion based on the Burgers' equation. Our PSpice model allowed studying the temporal profile of the ultrasonic wave during its propagation. The simulation results are compared to the analytical solution of the burgers' equation showing the validity of the model.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130640513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Frequency domain simulation of lossy multiconductor transmission lines 损耗多导体传输线的频域仿真
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418620
Youssef Mejdoub, H. Rouijaa, A. Ghammaz
{"title":"Frequency domain simulation of lossy multiconductor transmission lines","authors":"Youssef Mejdoub, H. Rouijaa, A. Ghammaz","doi":"10.1109/ICM.2009.5418620","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418620","url":null,"abstract":"In this paper, we present the behaviour of the lossless and lossy multiconductor transmission lines in frequency domain. This study is based on a characteristics method, this method is permits modeling the line as a quadripole whose advantage is not to presuppose applied charges conditions in its extreme. This permits it to be introduced easily in the circuit simulators as Spice, Esacap and Saber. Diverse examples of applications, in the literature, are presented to validate these method and to show their interests and to understand the behaviour of a line MTL in the frequency domain.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129764860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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