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2009 International Conference on Microelectronics - ICM最新文献

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A 10Gb/s Backplane decision feedback equalizer in 90nm-CMOS technology 基于90nm cmos技术的10Gb/s背板决策反馈均衡器
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418656
O. Hatem, M. Dessouky, A. E. Hennawy
{"title":"A 10Gb/s Backplane decision feedback equalizer in 90nm-CMOS technology","authors":"O. Hatem, M. Dessouky, A. E. Hennawy","doi":"10.1109/ICM.2009.5418656","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418656","url":null,"abstract":"This paper presents the design of a 10-Gb/s decision feedback equalizer (DFE) for chip-to-chip communications in 90-nm CMOS technology. A fast slicer architecture is proposed that achieves timing constraints without the use of speculation techniques. Removing speculation improves power consumption by 60%. The 5-tap topology was found optimum to compensate for channel losses up to 22 dB. A half-rate architecture is used to enable operation at 10-Gb/s. The DFE system consumes 43 mW from a 1.2 V supply, and occupies an area of 177µm ∗ 146µm. Post-layout simulations done using a channel with 22dB loss at 5 GHz, demonstrate the effectiveness of the DFE equalization.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122391077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of intrinsic parameter fluctuation on the fault tolerance of L1 data cache 本征参数波动对L1数据缓存容错性的影响
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418676
R. A. Ahmed, K. Samsudin, F. Rokhani
{"title":"Impact of intrinsic parameter fluctuation on the fault tolerance of L1 data cache","authors":"R. A. Ahmed, K. Samsudin, F. Rokhani","doi":"10.1109/ICM.2009.5418676","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418676","url":null,"abstract":"As the semiconductor process technology continues to scale deeper into the nanometer region, the intrinsic parameter fluctuations will aggressively affect the performance and reliability of future microprocessors and System-on-Chip (SoC) applications. These system requires large SRAM arrays that occupy an increasing fraction of the chip real estate. To investigate the impact various source of intrinsic parameter fluctuation (IPF) from systems point of view, a framework to bridge architecture-level and device-level simulation will be utilized for data cache built from transistors with 25 nm, 18 nm and 13 nm technology node. This study found that the IPF will not have any significant impacts on data cache memory systems build with 25 nm while increasing the memory cell ratio, (β) to two will overcome the IPF impacts for the 18 nm. However, the 13 nm technology data cache could not operate even with higher cell ratio. Common, cache memory fault detection and correction such as ECC and redundancy can only partially remove the transaction error caused by these fluctuation sources.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115866464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The design of the novel BiCMOS ESD protection circuit with low trigger voltage and fast turn-on speed 设计了一种触发电压低、导通速度快的新型BiCMOS ESD保护电路
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418608
Yong-Seo Koo, Hyun-Duck Lee, Jae-Hwan Ha, Jae-Chang Kwak, Jong-Kee Kwon
{"title":"The design of the novel BiCMOS ESD protection circuit with low trigger voltage and fast turn-on speed","authors":"Yong-Seo Koo, Hyun-Duck Lee, Jae-Hwan Ha, Jae-Chang Kwak, Jong-Kee Kwon","doi":"10.1109/ICM.2009.5418608","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418608","url":null,"abstract":"In this paper, the design of the novel BiCMOS ESD protection circuit with low trigger voltage and fast turn-on speed is proposed. The proposed ESD protection circuit is verified by the transmission line pulse system. The results show that the novel BiCMOS ESD protection circuit has lower trigger voltage of 5.98V compared with that of conventional GGNMOS. And this ESD protection circuit has faster turn-on time of about 37ns than that of the conventional substrate-triggered ESD protection circuit. Also, the ESD protection circuit pass the ESD of HBM 3.2kV and MM 210V.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"382 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122777071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Amplitude of RTS noise in MOSFETs mosfet中RTS噪声的幅值
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418614
J. Pavelka, J. Sikula, M. Tacano, M. Toita
{"title":"Amplitude of RTS noise in MOSFETs","authors":"J. Pavelka, J. Sikula, M. Tacano, M. Toita","doi":"10.1109/ICM.2009.5418614","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418614","url":null,"abstract":"Low frequency noise of NMOS and PMOS field effect transistors was measured in wide temperature range as a function of applied electric field intensity in longitudinal and perpendicular direction and the influence of sample geometry on 1/f noise and RTS noise was examined for various gate lengths. Relative amplitude of RTS noise given by number of carriers under the gate and its dependence on channel and gate bias was analyzed.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122870471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new approach of a precise electric modeling of the semiconductors and dielectrics 半导体和电介质精确电建模的新方法
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418644
A. Malaoui, E. Bendada, M. Mabrouki, M. Ankrim, K. Quotb
{"title":"A new approach of a precise electric modeling of the semiconductors and dielectrics","authors":"A. Malaoui, E. Bendada, M. Mabrouki, M. Ankrim, K. Quotb","doi":"10.1109/ICM.2009.5418644","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418644","url":null,"abstract":"A new method is developed in this work, to seek precise and simple electric models of physical samples. This technique is based on the decomposition of the electric impedance in a series of the elementary electrical circuits. Algorithm and software programs are developed to estimate the order and the number of these basic circuits. Tests are applied on a BST ceramics and Schottky junction. The founding electric models are compared with other models, often used in the literature. Interesting results are observed on the level of the statistical errors and the various significant elements of the models.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123073430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 10 GHz ring VCO using a wide range delay cell architecture 采用宽范围延迟单元结构的10ghz环形VCO
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418658
S. A. ElKader, M. Dessouky
{"title":"A 10 GHz ring VCO using a wide range delay cell architecture","authors":"S. A. ElKader, M. Dessouky","doi":"10.1109/ICM.2009.5418658","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418658","url":null,"abstract":"A wide range ring voltage-controlled oscillator (VCO) operating in the range 1–10 GHz is proposed. The design uses a modified delay cell architecture optimized to work on a wide frequency range. The VCO is designed on a 90 nm technology, consumes around 6.3 mW from a 1 V supply. It occupies an area of 18.5µ×35µ. Post-layout simulations confirm the wide tuning range of the VCO.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123551659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Modelling real photovoltaic solar cell using Maple 使用Maple建模真实的光伏太阳能电池
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418600
S. Aazou, E. Assaid
{"title":"Modelling real photovoltaic solar cell using Maple","authors":"S. Aazou, E. Assaid","doi":"10.1109/ICM.2009.5418600","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418600","url":null,"abstract":"In this paper, Maple software is used to study a solar cell modelled by an electronic circuit containing five physical parameters. The physical parameters are: the series resistance, the shunt resistance, the diode reverse saturation current, the diode ideality factor and the photocurrent (see figure 1). First, the characteristic equation is solved in order to find the output current as a function of the output voltage of the solar cell. Second, the expressions of the short circuit current, the open circuit voltage, the dynamical resistance of the solar cell and different kinds of powers involved: the output power, the power dissipated by Joule Effect in the internal components of the solar cell and the solar cell total power are determined analytically. Finally, the effects of the different physical parameters on the characteristic and on the delivered power of the solar cell are studied and analyzed.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128067039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Mixed-signal design methodology for continuous-time quadrature bandpass ΔΣ modulator 连续时间正交带通ΔΣ调制器的混合信号设计方法
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418679
N. Jouida, C. Rebai, A. Ghazel, D. Dallet
{"title":"Mixed-signal design methodology for continuous-time quadrature bandpass ΔΣ modulator","authors":"N. Jouida, C. Rebai, A. Ghazel, D. Dallet","doi":"10.1109/ICM.2009.5418679","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418679","url":null,"abstract":"Continuous-time (CT) quadrature bandpass (QBP) delta-sigma (ΔΣ) modulator is already in itself a mixed-signal system. That fact creates a discontinuity in the traditional IC design flow which assumes that “discrete” and “continuous” time domain designs require separate design tools. This paper presents an efficient top-down methodology for mixed-signal design. We report the design process from the system-level down to gate/transistor-level; modeling and simulation are applied to the ΔΣ modulator. We have verified the robustness and effectiveness of our approach which resulted in shorter design process cycles and higher rates of success.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128124886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the design of a low noise readout circuit for in-vivo dosimeter 体内剂量计低噪声读出电路的设计
2009 International Conference on Microelectronics - ICM Pub Date : 2009-12-01 DOI: 10.1109/ICM.2009.5418587
A. E. Mourabit, G. Lu, P. Pittet
{"title":"On the design of a low noise readout circuit for in-vivo dosimeter","authors":"A. E. Mourabit, G. Lu, P. Pittet","doi":"10.1109/ICM.2009.5418587","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418587","url":null,"abstract":"The paper presents a readout circuit associated with photodiodes dedicated to an in-vivo dosimeter. The circuit consists of a fully differential charge sensitive amplifier (CSA) stage, a differential-to-single-ended amplifier stage and a buffered double sampling stage. The CSA implements a switched integration method to minimize dark current contribution to integrated output signal. Its fully differential operation rejects charge injection effect and further cancels dark current effect. Noise analysis is performed to identify main parameters for low-noise design. The double sampling stage is operated by non correlated double sampling (NCDS) to effectively reduce 1/f noise. The circuit operation is validated by transistor-level simulations.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116808054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Using discrete-variable optimization for CMOS spiral inductor design 用离散变量优化方法进行CMOS螺旋电感的设计
2009 International Conference on Microelectronics - ICM Pub Date : 1900-01-01 DOI: 10.1109/ICM.2009.5418617
P. Pereira, M. Fino, F. Coito
{"title":"Using discrete-variable optimization for CMOS spiral inductor design","authors":"P. Pereira, M. Fino, F. Coito","doi":"10.1109/ICM.2009.5418617","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418617","url":null,"abstract":"In this paper a discrete-variable optimization methodology for the automatic design of CMOS integrated spiral inductors is introduced. The use of discrete variable optimization procedure offers the designer the possibility for exploring the design space exclusively in those points available for the technology under use. Further user-defined constraints between layout parameters may also be incorporated as a way of taking into account design heuristics. A comparison between using discrete-variable optimization and a continuous optimization procedure followed by a discretization of the results is presented, where the benefits of the proposed methodology are presented. An application using the proposed methodology was developed in Matlab and the optimization toolbox is used. For the sake of simplicity the π-model has been used for characterizing the inductor. The validity of the design results is checked against circuit simulation with ASITIC.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"18 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116401144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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