{"title":"基于纳米器件架构的功能映射","authors":"M. Amadou, S. Le Beux, G. Nicolescu, I. O’Connor","doi":"10.1109/ICM.2009.5418665","DOIUrl":null,"url":null,"abstract":"Recently, technology advancement led to the emergence of nanodevice-based architectures. By exploiting the fine-grain dynamic reconfigurability of these logic cells, nanodevice-based architectures are expected, compared to conventional architectures, to reduce area and cost, and improve performance over a broad range of applications. In order to explore the potential of these architectures, the definition of new CAD tools is required. This paper discusses the challenges for system-level exploration for nanodevice-based architectures and proposes an approach enabling automatic application partitioning and mapping for these architectures.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Functional mapping for nanodevice-based architectures\",\"authors\":\"M. Amadou, S. Le Beux, G. Nicolescu, I. O’Connor\",\"doi\":\"10.1109/ICM.2009.5418665\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recently, technology advancement led to the emergence of nanodevice-based architectures. By exploiting the fine-grain dynamic reconfigurability of these logic cells, nanodevice-based architectures are expected, compared to conventional architectures, to reduce area and cost, and improve performance over a broad range of applications. In order to explore the potential of these architectures, the definition of new CAD tools is required. This paper discusses the challenges for system-level exploration for nanodevice-based architectures and proposes an approach enabling automatic application partitioning and mapping for these architectures.\",\"PeriodicalId\":391668,\"journal\":{\"name\":\"2009 International Conference on Microelectronics - ICM\",\"volume\":\"93 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Conference on Microelectronics - ICM\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2009.5418665\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Microelectronics - ICM","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2009.5418665","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Functional mapping for nanodevice-based architectures
Recently, technology advancement led to the emergence of nanodevice-based architectures. By exploiting the fine-grain dynamic reconfigurability of these logic cells, nanodevice-based architectures are expected, compared to conventional architectures, to reduce area and cost, and improve performance over a broad range of applications. In order to explore the potential of these architectures, the definition of new CAD tools is required. This paper discusses the challenges for system-level exploration for nanodevice-based architectures and proposes an approach enabling automatic application partitioning and mapping for these architectures.