用于单电子电路仿真的SPICE宏观模型

M. Karimian, M. Dousti, M. Pouyan, R. Faez
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引用次数: 19

摘要

本文提出了一种新的更精确的单电子晶体管(set)仿真宏观模型。此外,该模型还包括电子隧穿时间的计算能力。在我们提出的模型中,我们对以前的模型进行了修改,并对它们的公式进行了一些基本的修正。除了实现更高的精度外,我们还增加了一个开关电容电路,作为量化器,以评估电子穿过势垒的时间。我们使用HSPICE进行高速仿真,并观察到与SIMON 2.0相比,我们的宏观模型给出的结果比其他模型更准确。该模型完全适用于计算复杂电路的延迟时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A new SPICE macro-model for simulation of single electron circuits
In this paper we have proposed a new and more accurate macro-model for simulation of single electron transistors (SETs). Furthermore, this model includes the ability of electron tunneling time calculation. In our proposed model, we have modified the previous models and applied some basic corrections to their formulas. In addition to achievement of more accuracy, we have added a switched capacitor circuit, as a quantizer, to evaluate the time of electron tunneling through the barrier. We used HSPICE for high-speed simulation and observed that our macro-model gives more accurate results than of the other models when compare with SIMON 2.0. This model is completely applicable for calculating the delay time of complicated circuits.
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