{"title":"System analysis of 2.4 GHz IEEE 802.15.4 compliant frequency synthesizer","authors":"N. M. Ismail, M. Othman","doi":"10.1109/ICM.2009.5418653","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418653","url":null,"abstract":"This paper presents a detailed system design of PLL frequency synthesizer. The PLL is designed for 2.4 GHz unlicensed industrial, scientific, and medical band (ISM band) IEEE 802.15.4 Zigbee transceiver. The PLL system analysis is meant for Zero-IF transceiver. Hand calculations and assumptions are discussed then validated by ADS (Advanced Design System) simulations.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132750739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A programmable true piecewise approximation logarithmic amplifier","authors":"M. Shaterian, A. Abrishamifar, H. Shamsi","doi":"10.1109/ICM.2009.5418580","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418580","url":null,"abstract":"This paper describes the operation theory, mathematical analysis and simulation of parallel summation type of the true piecewise approximation logarithmic amplifiers. It also reports a programmable logarithmic amplifier to have a desired logarithmic characteristic in special applications. To design the programmable structure, mathematical analysis of parallel summation type of the true piecewise approximation logarithmic amplifier is performed and based on it, a new method for improving its characteristic and some methods for adding flexibility and programmability to the structure is described. The presented programmable logarithmic architecture can be used in applications with variant and uncertain input signal range such as wide range wireless receivers and radar applications and some analog signal processing applications.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132239953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of triple-mode Digital Down Converter for WCDMA, CDMA2000 and GSM of Software Defined Radio","authors":"Emad S. Malki, K. Shehata, A. Madian","doi":"10.1109/ICM.2009.5418631","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418631","url":null,"abstract":"Software-Defined Radio (SDR) is a rapidly evolving technology. SDR have been widely studied as a solution to support multiple competing and in compatible air interface standard in future wireless communications. In this paper, we present the design of a Digital Down Converter (DDC) module for triple-mode WCDMA, CDMA2000 and GSM. The designed module consists of digital mixer, CIC filter, and decimation filter and frequency converter. Theses sub-modules are software reconfigured in architecture to be compatible with WCDMA, CDMA2000 and GSM. The design is software configured with minimum hardware and maximum operating speed.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132305826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Bendada, A. Malaoui, M. Mabrouki, K. Quotb, K. Rais
{"title":"Annealing of Irradiated-Induced defects in power MOSFETs","authors":"E. Bendada, A. Malaoui, M. Mabrouki, K. Quotb, K. Rais","doi":"10.1109/ICM.2009.5418641","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418641","url":null,"abstract":"An innovative method of device characterization is experimented to qualify annealing Gamma-ray damage in power MOSFETs. The degradation of structural parameters of the body-drain junction for a dose rate of 103.8 rad.mn-1 is presented. Temperature annealing effects, at 100°C, are discussed and analyzed against the evolution of the density trapped oxide and interface charges.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115176415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient FPGA implementation for the IEEE 802.16e interleaver","authors":"A. A. Khater, M. Khairy, S. Habib","doi":"10.1109/ICM.2009.5418660","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418660","url":null,"abstract":"In this paper, we implement and evaluate a novel design for the hardware of the multi-mode interleaver block used in the OFDMA mode of the IEEE 802.16e (Mobile WiMAX) standard. A new architecture that is both area and delay efficient is introduced. The area and delay efficiency of this new architecture is verified via quantitative comparisons between FPGA implementations of this architecture and classical interleaver designs.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116571881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Scaling the bulk-driven MOSFET","authors":"Christopher Urban, J. Moon, P. R. Mukund","doi":"10.1109/ICM.2009.5418591","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418591","url":null,"abstract":"This paper investigates the impact of device scaling on the bulk-driven MOSFET. In particular, the behavior of gmb is observed across process technology and it is shown that the gmb/gm ratio falls from 0.38 to 0.12 between IBM's 0.25 μm and 65 nm bulk CMOS processes via simulation. Delta and step doping are then proposed to enable the scaling of bulk-driven MOSFETs down to a channel length of 80 nm on a one volt supply. Using 2-D device simulations in ATLAS, it is shown that the intrinsic gain of a bulk-driven MOSFET can be enhanced by as much as 78% for a step doping profile and 106% for a delta doping profile in an NMOS device when compared to a uniform substrate.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"228 0 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126033445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. E. Naimi, B. Hajji, Y. Habbani, I. Humenyuk, J. Launay, P. Temple-Boyer
{"title":"Modeling of the pH-ISFET thermal drift","authors":"S. E. Naimi, B. Hajji, Y. Habbani, I. Humenyuk, J. Launay, P. Temple-Boyer","doi":"10.1109/ICM.2009.5418627","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418627","url":null,"abstract":"The temperature effect on pH-ISFET response has been modeled by taking into account the dependence with temperature of the dissociation constants Ka, Kb at the SiO2/Si3N4 electrolyte/insulator interface. The relationship of Ka, Kb versus the temperature is implemented in the development model based in the site-binding model combined with the level 3 of PSPICE model of MOSFET. The model parameters were extracted using genetic algorithm and the simulations results using these values showed a good fit between modeling and experimental data on a large temperature range.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"117 20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126406917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Prabhleen K. Kalkat, R. Sedaghat, Jalal Mohammad Chikhe, Reza Javaheri
{"title":"Soft error injection using advanced switch-level models for combinational logic in nanometer technologies","authors":"Prabhleen K. Kalkat, R. Sedaghat, Jalal Mohammad Chikhe, Reza Javaheri","doi":"10.1109/ICM.2009.5418615","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418615","url":null,"abstract":"Due to technology scaling, modern digital systems are becoming more prone to single-event transients (SETs) caused by radiation strikes in CMOS logic devices. This has led to the need for better soft error detection methods in order to increase the reliability of logic circuits in nanometer technologies. Present day soft error detection techniques assume that soft errors occur due to voltage pulses which change the logic state of a transistor node. A novel soft error detection concept is used, assuming that voltage fluctuations smaller than logic threshold can eventually result in soft errors. Advanced switch-level models were designed which mimic important characteristics of transistor-level circuits like bidirectional signal flow, driving strength variations and node capacitances and use verilog driving strengths to model different voltage values. The resulting switch-level models eliminate the complexity associated with state-of-art transistor level simulators while achieving desired amount of accuracy and faster simulation. The aim of this paper is to interpret various parameters used in these strength-based switch models in order to find an efficient way of injecting transients into complex logic circuits. The approach has been evaluated experimentally by creating a simulation environment which allows transient injection at internal nodes of switch-level circuits and injecting a wide range of input test vectors to ISCAS'85 benchmarks. The simulation results show that transient injection at drains of switch-level circuits gives better results in terms of accuracy and prevents over-estimation of soft error rate calculations as compared to injection at gates of transistors.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127839862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tarun Chawla, Sébastien Marchal, A. Amara, A. Vladimirescu
{"title":"Pulse width degradation in 45nm ASIC design due to global and environmental variations","authors":"Tarun Chawla, Sébastien Marchal, A. Amara, A. Vladimirescu","doi":"10.1109/ICM.2009.5418624","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418624","url":null,"abstract":"Global and Environmental variations together are responsible for differences in timing from one die to another for an ASIC design. The tried and tested method of corners and margins is still the dominant method in ASIC industry to assure the timing characteristics of a design. However, the increasing margins limit the scaling of maximum achievable frequency for a given die size, especially because of minimum pulse width violation. The importance of clock tree pulse-width variations due to global N-to-P mismatch is increasing with decreasing pulse width. To continue scaling the clock frequency, we may need to make application specific margins and corners. In this work, we have estimated the impact of pulse width variations on standard cells in a clock library using industrial models and spice simulations. We found that by unbalancing the first stage of a cell with respect to rise and fall edge in a multiple supply voltage design, we could halve the pulse width variations with minimal effect on delay and slew.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115199672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. S. Abdellatif, A. E. Rouby, Mohamed B. Abdelhalim, A. Khalil
{"title":"Interconnects parasitic extraction using modified Genetic Algorithm","authors":"A. S. Abdellatif, A. E. Rouby, Mohamed B. Abdelhalim, A. Khalil","doi":"10.1109/ICM.2009.5418622","DOIUrl":"https://doi.org/10.1109/ICM.2009.5418622","url":null,"abstract":"Three new Genetic Algorithm (GA) are proposed and used to solve a Curve fitting problem for Parasitic Extraction Macro-modeling application. The first proposed approach, Diagonal GA (DGA); is based on replacing the traditional random population initialization method with a deterministic diagonal-like one. The second proposed approach, Elite Condensation GA (ECGA); is based on fine tuning the GA by explicitly condensing the population around a number of elite individuals. The third proposed approach, ECGA2, is a modified version of ECGA; that chooses elite members among all the population in each generation, then it divides the population into a number of sub-populations where each sub-population is composed of a single elite and a condensed population around it. Then, it performs GA operations on each of those subpopulations separately before merging them all into one population and keep repeating that divide-merging sequence. The performances of these three proposed approaches were measured on an extensive real data sets and used along with the understanding of the physical problem to offer various explanations of the theoretical aspects of the new algorithms.","PeriodicalId":391668,"journal":{"name":"2009 International Conference on Microelectronics - ICM","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130703610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}