Soft error injection using advanced switch-level models for combinational logic in nanometer technologies

Due to technology scaling, modern digital systems are becoming more prone to single-event transients (SETs) caused by radiation strikes in CMOS logic devices. This has led to the need for better soft error detection methods in order to increase the reliability of logic circuits in nanometer technologies. Present day soft error detection techniques assume that soft errors occur due to voltage pulses which change the logic state of a transistor node. A novel soft error detection concept is used, assuming that voltage fluctuations smaller than logic threshold can eventually result in soft errors. Advanced switch-level models were designed which mimic important characteristics of transistor-level circuits like bidirectional signal flow, driving strength variations and node capacitances and use verilog driving strengths to model different voltage values. The resulting switch-level models eliminate the complexity associated with state-of-art transistor level simulators while achieving desired amount of accuracy and faster simulation. The aim of this paper is to interpret various parameters used in these strength-based switch models in order to find an efficient way of injecting transients into complex logic circuits. The approach has been evaluated experimentally by creating a simulation environment which allows transient injection at internal nodes of switch-level circuits and injecting a wide range of input test vectors to ISCAS'85 benchmarks. The simulation results show that transient injection at drains of switch-level circuits gives better results in terms of accuracy and prevents over-estimation of soft error rate calculations as compared to injection at gates of transistors.