He Tang, H Zhao, Xin Wang, Lin Lin, Q. Fang, Jian Liu, Albert Z. H. Wang, S. Fan, B. Zhao, Zitao Shi, Yuhua Cheng
{"title":"Capacitive interpolated Flash ADC design technique","authors":"He Tang, H Zhao, Xin Wang, Lin Lin, Q. Fang, Jian Liu, Albert Z. H. Wang, S. Fan, B. Zhao, Zitao Shi, Yuhua Cheng","doi":"10.1109/SOCDC.2010.5682945","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682945","url":null,"abstract":"Analog-to-digital converter (ADC) is a key component electronic system. Flash ADC is widely used in high-speed systems. However, practical flash ADC design is very challenging where experience plays a significant role. ADC design involves in many factors at different levels including architecture, circuit, device and technology. This paper reports a quantitative design methodology for capacitive interpolated flash ADCs, which establishes a design matrix that links ADC chip performance with architecture, block circuit, devices and process parameters. Complex relationship among critical ADC specs, such as, sampling speed, interpolation factors, number of stages, preamplifier bandwidth and transistor parasitic effects, etc, are described. An accurate dynamic power analysis technique is depicted. This flash ADC design method was validated using several designs in 90nm and 130nm CMOS technologies.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"649 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132022527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jinyong Lee, Seungjun Yang, Sanghyun Park, Ingoo Heo, Y. Paek
{"title":"VLIW processor for H.264: Integer transform and Quantization","authors":"Jinyong Lee, Seungjun Yang, Sanghyun Park, Ingoo Heo, Y. Paek","doi":"10.1109/SOCDC.2010.5682944","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682944","url":null,"abstract":"As the performance of mobile devices increases, a demand for watching high quality videos in those devices also increases. VLIW (Very Long Instruction Word) processors have been used as a coprocessor to accelerate the performance of various CODECs in the embedded systems, e.g. TI Davinci, but the general VLIW has too much redundancies if the applications required to be executed on the VLIW are restricted. In this paper, we propose a VLIW processor focused on the DCT and Quantization of H.264. Our proposed architecture has 4 issue slots and 16 bit width data path which is half of the TI's TMS320C6× series, but performs better than the TMS320C6× series in terms of cycle count and throughput.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125215046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Cho, Bongsub Song, Kwangsoo Kim, J. Burm, Sang-Wook Han
{"title":"A VGA CMOS Image Sensor with 11-bit column parallel single-slope ADCs","authors":"N. Cho, Bongsub Song, Kwangsoo Kim, J. Burm, Sang-Wook Han","doi":"10.1109/SOCDC.2010.5682981","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682981","url":null,"abstract":"In this paper, CMOS Image Sensor (CIS) for VGA is presented. It has 11-bit column parallel single-slope ADCs. Single slope ADC is suitable for column parallel ADC of CIS. This CIS is fabricated in 0.13μm CMOS process. Its pixel size is 2.25 × 2.25 μm2. Total chip area is 5×5 mm. Its analog power consumption is 42.9 mW and digital power consumption is 1.6 mW.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121789479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Model-based SoC design using ESL environment","authors":"Dai Araki, A. Nakamura, M. Miyama","doi":"10.1109/SOCDC.2010.5682968","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682968","url":null,"abstract":"With the rising complexities of SoC (Systems-on-Chip), the design community has been searching for new methodology that can handle the given complexities with increased productivity and decreased times-to-market. Electronic system-level (ESL) design is becoming a promised key solution in SoC design, software and hardware must be developed together, however, both software and hardware designers have different views of the system and they use different design/modeling techniques and tools. In this paper, we show an integrated ESL environment for model-based SoC design which supports from algorithm specification modeling by Simulink and synthesizing both software and hardware of SoC by using the combination of several commercialized ESL tools. We also show the design case of video autofocus control unit for the security camera system by using the ESL environment.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122417542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel leakage power reduction technique for CMOS circuit design","authors":"J. Chun, C. Y. Roger Chen","doi":"10.1109/SOCDC.2010.5682957","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682957","url":null,"abstract":"Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit types for low-power design centered around inserting controlling transistors between pull-up and pull down circuits as well as between pull-up circuits/pull down circuits and power/ground. We investigate the characteristics of proposed gate types in terms of ability to reduce power consumption and their associated delay overhead. In addition, several variations of drain gating are discussed. In the end, an overall procedure for low-power circuit design is proposed by intelligently mixing various proposed circuit types for gates in the circuits based upon gate criticality analysis. Extensive SPICE simulation results were reported using 45nm, 32nm and 22nm process technologies. Significant power reduction is achieved with zero or little increase in the critical path delay of the overall circuits.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116728048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Donghoon Yeo, Ehsan ul haq, Jongdae Kim, Mirza Waqar Baig, Hyunchu Shin
{"title":"Adaptive bilateral filtering for noise removal in depth upsampling","authors":"Donghoon Yeo, Ehsan ul haq, Jongdae Kim, Mirza Waqar Baig, Hyunchu Shin","doi":"10.1109/SOCDC.2010.5682980","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682980","url":null,"abstract":"3D scene rendering requires depth maps and color information to produce high quality 3D results. Unfortunately, depth maps captured with the Time-of-flight (TOF) cameras have limited resolution and poor image quality, being severely influenced by the random and systematic noise, which makes them inapposite for generating high quality 3D images. In this paper, we have further analyzed a framework for upsampling the resolution of depth maps that jointly uses Gaussians of spatial and depth differences of low resolution depth map's pixels along with Gaussian of color intensity difference from high resolution 2D color image of the same scene. The variance of the Gaussian functions controls the amount of smoothing in uni-planner area and sharpness at boundaries. Using bigger variance smooths uni-planner area but blurs edges and vice versa. We have devised a method to adaptively calculate and use variance to get smoother surface and sharper edges of upsampled depth map with minimized noise.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116751514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MPW implementation of integer-pixel motion estimation circuit for 1080HD video encoder","authors":"Gyung-Sil Park, Kyeongsoon Cho","doi":"10.1109/SOCDC.2010.5682878","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682878","url":null,"abstract":"We propose a new H.264 integer-pixel motion estimation algorithm and circuit architecture to improve the processing speed. The proposed circuit supports 7 kinds of variable block sizes and generates 41 motion vectors. Our circuit based on the proposed algorithm and architecture processes 60 image frames per second for 1080HD video at the operating frequency of 45.5MHz. We implemented an MPW chip using 180nm standard cell library for silicon verification.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115019417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Algorithms for rare event analysis in nano-CMOS circuits using statistical blockade","authors":"Luo Sun, J. Mathew, D. Pradhan, S. Mohanty","doi":"10.1109/SOCDC.2010.5682948","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682948","url":null,"abstract":"Accurate and fast characterization of the process variations of nano-CMOS circuits is becoming increasingly important for design for manufacturing (DFM) with highest yield. One of the ways to understand the circuit behavior under the process variations is to analyze the rare events that may happen due to such process variations. The Statistical Blockade (SB) is a approach for such rare events analysis. In SB, the classification threshold selection becomes very important for different tail regions which is related to the number of rare events simulation. This paper presents the values of classification threshold for different tail regions of typical circuits. It is shown that a given classifier requires different number of training samples depending on classification thresholds.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128803193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuko Hara-Azumi, Toshinobu Matsuba, H. Tomiyama, S. Honda, H. Takada, N. Dutt
{"title":"Towards practical high-level synthesis from large behavioral descriptions","authors":"Yuko Hara-Azumi, Toshinobu Matsuba, H. Tomiyama, S. Honda, H. Takada, N. Dutt","doi":"10.1109/SOCDC.2010.5682969","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682969","url":null,"abstract":"This paper presents two sets of our recent works towards practical high-level synthesis from large behavioral descriptions: one optimally partitions input behavioral descriptions considering the controller's complexity of synthesized circuits, and the other enhances clock frequency of the circuits by aggressively removing MUXs inserted before registers. These works can further advance the high-level synthesis technology.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130930604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nerual signal recorder with tunable gain amplifier using low transconductance OTA","authors":"DaeHoon Na, Tae Wook Kim","doi":"10.1109/SOCDC.2010.5682978","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682978","url":null,"abstract":"In this paper, multi-channel neural signal recorder with tunable gain filter is proposed. It is characterized by small-gm OTA for lowering cutoff frequency. The prototype of the proposed system is designed in TSMC 0.18 μm CMOS technology. Filter consists of high pass filter of delta-gm structure OTA with 201.06 pA/V transconductance and tunable gain Gm-C low pass filter. Single slope ADC is used to convert filter output into dig-ital bits. The tunable gain range, bandwidth, CMRR and input referred noise of resulting filter are 20–68 dB, 20 Hz–10 kHz, 185.7 dB at 5 kHz and 319 nV/VHz, respectively. Single slope ADC has 40 kS/s sampling rate and 1.2 V input range. Total power consumption per channel is 59 μW.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129688535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}