2010 International SoC Design Conference最新文献

筛选
英文 中文
Low-complexity design of PHY/MAC modem processor for WiMedia UWB systems WiMedia UWB系统PHY/MAC调制解调器处理器的低复杂度设计
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682953
Sangmin Lee, Taewook Chung, Kilhwan Kim, Chulho Chung, Young-Ho Jung, Jaeseok Kim
{"title":"Low-complexity design of PHY/MAC modem processor for WiMedia UWB systems","authors":"Sangmin Lee, Taewook Chung, Kilhwan Kim, Chulho Chung, Young-Ho Jung, Jaeseok Kim","doi":"10.1109/SOCDC.2010.5682953","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682953","url":null,"abstract":"We propose a low-complexity design and implementation for baseband modem processors in WiMedia UWB systems. The proposed processor is a MAC-PHY integrated baseband processor that complies with Standard 1.1 (ECMA368/369) and supports full mode up to 480 Mbps. It realizes low power and low area by adopting 4-parallel structures to decrease operating frequency. It was implemented with a CMOS 0.13 μm process, has an operating frequency of 152 MHz, and was synthesized with approx. 1.6M gates.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125804654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A robust pulse delay circuit utilizing a differential buffer ring 一种利用差分缓冲环的鲁棒脉冲延迟电路
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682920
Jaehyun Jeong, T. Iizuka, T. Nakura, M. Ikeda, K. Asada
{"title":"A robust pulse delay circuit utilizing a differential buffer ring","authors":"Jaehyun Jeong, T. Iizuka, T. Nakura, M. Ikeda, K. Asada","doi":"10.1109/SOCDC.2010.5682920","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682920","url":null,"abstract":"In this paper, we propose a pulse delay circuit using a differential buffer ring. The proposed circuit keeps an input pulse propagating on the buffer ring without a degradation of pulse width information. The cross-coupled buffer ring with compensating inverters improves the tolerance to the process variation. The proposed circuit has been implemented using 65nm CMOS process, and the simulation results demonstrate that the proposed circuit keeps an input pulse width independent of the process corner conditions, and the measurement results show that the proposed pulse delay circuit using differential buffer ring is more robust to the process variability than conventional buffer ring.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"455 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125847741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Heterogeneous integration of 1-D nanomaterials for electronic circuitry 电子电路中一维纳米材料的非均质集成
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682926
Yun-Ze Long, C. Johnny, Z. Fan
{"title":"Heterogeneous integration of 1-D nanomaterials for electronic circuitry","authors":"Yun-Ze Long, C. Johnny, Z. Fan","doi":"10.1109/SOCDC.2010.5682926","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682926","url":null,"abstract":"One-dimensional (1-D) nanomaterials have been extensively explored as the potential building blocks for a variety of electronic and optoelectronic applications due to the continuous increasing demand for miniaturized devices and circuits. In addition, this category of materials possesses a number of unique properties different from bulk materials, such as excellent flexibility, high surface-to-volume ratio, etc., which make them attractive for applications in flexible electronics, sensors, and so on. Nevertheless, controlled and uniform assembly of synthetic 1-D materials with high scalability is still one of the major bottleneck challenges towards the materials and device integration for circuit applications. Here we illustrate the large-scale heterogeneous assembly of highly ordered arrays of organic and inorganic 1-D materials via electrospinning and contact printing methods. These innovative approaches enable the control of the ordering and packing density of 1-D nanomaterials in a significant degree, thus are versatile for the design and implementation of novel electronic circuitry. In particular, we have configured assembled inorganic 1-D materials as a variety of functional electronic and optoelectronic devices, including field-effect transistors, Schottky diodes and photodiodes on both rigid and flexible substrates. Furthermore, we have fabricated and characterized an all-nanowire integrated image sensor. This demonstrates that these functional components can be heterogeneously integrated together to implement nanomaterial-based circuitry.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A random number generator for low power cryptographic application 一个用于低功耗加密应用的随机数生成器
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682906
Jingjing Lan, W. Goh, Z. Kong, K. Yeo
{"title":"A random number generator for low power cryptographic application","authors":"Jingjing Lan, W. Goh, Z. Kong, K. Yeo","doi":"10.1109/SOCDC.2010.5682906","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682906","url":null,"abstract":"Random number generator (RNG) is widely used in cryptographic system as the cryptographic keys generator. These keys are the most important component in the system since the security of the cryptographic system relies entirely on its quality. As digital circuit becomes faster and smaller, some of the desired properties a RNG should have are low-power and good statistical quality. This paper presents a low energy consumption RNG including a serial-to-parallel shift register, a 32-bit register and a pseudo random number generator (PRNG) module. The design can be implemented completely in digital circuit and requires no external components. A prototype was implemented using Chartered Semiconductor 0.18 μm CMOS technology and the power consumption was less than 5 mW. The random sequence produced by the proposed architecture has good statistical properties based on National Institute of Standards and Technology (NIST) statistical test. This RNG can be used to improve the performances such as flexibility and power consumption in communication device and cryptographic application.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116848640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Web-based CAD framework for low cost SoC design prototyping 基于web的CAD框架,用于低成本SoC设计原型
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682912
Taewan Kim, Sang-Hoon Hong, Yunmo Chung, Inhag Park
{"title":"Web-based CAD framework for low cost SoC design prototyping","authors":"Taewan Kim, Sang-Hoon Hong, Yunmo Chung, Inhag Park","doi":"10.1109/SOCDC.2010.5682912","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682912","url":null,"abstract":"In this paper, we propose a framework that allows an efficient way of designing and verifying an SoC. In particular, the proposed SoC design framework, which is based on the OpenRISC platform, utilizes the web environment to reduce the tooling costs while providing similar design times for a small work group. Expensive processing tasks, such as RTL level simulations and cross-compilations, are performed on the remote central server. The server also allows a user to share his or her IP libraries with different clients with user controllable library access permissions. The client is a 15MB program that performs and interfaces to all other tasks required for the SoC design. We demonstrate that the proposed server-client interface performs almost seamlessly.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Motion vector smoothing for motion-compensated frame rate up-conversion 运动补偿帧率上转换的运动矢量平滑
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682898
D. Yoo, Suk-ju Kang, Sung Kyu Lee, Young Hwan Kim
{"title":"Motion vector smoothing for motion-compensated frame rate up-conversion","authors":"D. Yoo, Suk-ju Kang, Sung Kyu Lee, Young Hwan Kim","doi":"10.1109/SOCDC.2010.5682898","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682898","url":null,"abstract":"In this paper, we propose a motion vector smoothing scheme for motion-compensated frame rate up-conversion. The proposed motion vector smoothing consists of three steps which are outlier detection, outlier correction, and motion vector refinement steps. The proposed method enhances the image quality of the interpolated frame by up to 0.88 dB, and the visual result of the proposed method is better than those of the benchmark methods","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121951691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and optimization of hybrid decoupling scheme for charge pump circuit in non-volatile memory application 非易失性存储器中电荷泵电路混合去耦方案的设计与优化
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682935
Mengshu Huang, Leona Okamura, T. Yoshihara
{"title":"Design and optimization of hybrid decoupling scheme for charge pump circuit in non-volatile memory application","authors":"Mengshu Huang, Leona Okamura, T. Yoshihara","doi":"10.1109/SOCDC.2010.5682935","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682935","url":null,"abstract":"A high area efficiency hybrid decoupling scheme using both passive and active capacitors is designed to suppress the program noise of charge pump in non-volatile memory. Through the decoupling impedance analysis and noise power calculation, an optimized ratio between the passive and active capacitors is obtained to achieve maximum noise suppression performance. The proposed hybrid decoupling charge pump is fabricated in 0.18μm technology with 1V supply voltage. The results show a nearly 20dB noise-suppression-ratio (NSR) to the conventional method and the ripple voltage reduction is 73%. The area overhead is only 2%.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129588467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of probabilistic-based Markov Random Field logic gates in 65nm CMOS technology 基于概率马尔可夫随机场的65纳米CMOS逻辑门设计
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682910
Zhenghao Lu, X. Yu, K. Yeo
{"title":"Design of probabilistic-based Markov Random Field logic gates in 65nm CMOS technology","authors":"Zhenghao Lu, X. Yu, K. Yeo","doi":"10.1109/SOCDC.2010.5682910","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682910","url":null,"abstract":"As the VLSI technology node is getting into the sub-100nm regime, the reliability issues caused by random interferences such as noise, process variations and manufacturing defects are changing the nature of digital computation from deterministic to probabilistic. This paper studies the principle of probabilistic-based Markov Random Field (MRF) design methodology for CMOS static logic gates. The MRF design technique is able to significantly improve the reliability and interference tolerance of the logic circuits. A Differential Cascode Voltage Switch (DCVS) based MRF logic design method is proposed, which presents substantial noise immunity improvement over the normal MRF logic circuits. The proposed method is validated by simulation in 65nm CMOS technology.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128067227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Thermal management via task scheduling for 3D NoC based multi-processor 基于3D NoC的多处理器任务调度的热管理
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682875
Han Wang, Yuzhuo Fu, Ting Liu, Jiafang Wang
{"title":"Thermal management via task scheduling for 3D NoC based multi-processor","authors":"Han Wang, Yuzhuo Fu, Ting Liu, Jiafang Wang","doi":"10.1109/SOCDC.2010.5682875","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682875","url":null,"abstract":"3D IC technology drives Network-On-Chip (NoC) design on towards 3D trend and relevant multi-core system further development. Thermal issue becomes more critical because of the increasing power density caused by 3D stack. OS-level task scheduling is an effective method to improve on-chip temperature condition. In this paper we propose a thermal management method using task scheduling to limit chip temperature under required constraints as well as consider performance degradation caused by moving task to a core far away from its data. A temperature controller is implemented in our simulator to determine temperature management actions. The result shows our algorithm has lower performance loss with the same temperature constraint compared to coldest and random scheduling.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117264121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
An Ultra-wideband transmitter with automatic self-calibration of sideband rejection up to 9 GHz in 65nm CMOS 一种超宽带发射机,在65nm CMOS中具有高达9 GHz的边带抑制自动自校准
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682903
Byoungjoong Kang, Jounghyun Yim, Taewan Kim, Heeseon Shin, Sangsoo Ko, Won Ko, Inhyo Ryu, Sung-Gi Yang, Wooseung Choo, Byeong-ha Park
{"title":"An Ultra-wideband transmitter with automatic self-calibration of sideband rejection up to 9 GHz in 65nm CMOS","authors":"Byoungjoong Kang, Jounghyun Yim, Taewan Kim, Heeseon Shin, Sangsoo Ko, Won Ko, Inhyo Ryu, Sung-Gi Yang, Wooseung Choo, Byeong-ha Park","doi":"10.1109/SOCDC.2010.5682903","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682903","url":null,"abstract":"An Ultra-wideband (UWB) transmitter is proposed that can correct phase errors in quadrature local (LO) signals automatically without help of baseband processor (BBP), operating from 3 to 9 GHz in 65 nm CMOS. The measured tuning range for sideband rejection is 32.7 dB at 7.7 GHz and 13.6 dB at 8.7 GHz. The measured EVM is lower than −20 dB for all supporting bands and TFCs (Time frequency codes) that are prescribed by WiMedia alliance. The power consumption of the transmitter including LO path and PLLs is 210 mW from a 1.2 V supply.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133311071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信