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2010 International SoC Design Conference最新文献

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An area efficient temperature sensor with software calibration for mobile application 一种适用于移动应用的具有软件校准功能的区域高效温度传感器
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682900
W. Hwang, Seoungjae Yoo, Hyungjong Ko, ByeongHa Park
{"title":"An area efficient temperature sensor with software calibration for mobile application","authors":"W. Hwang, Seoungjae Yoo, Hyungjong Ko, ByeongHa Park","doi":"10.1109/SOCDC.2010.5682900","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682900","url":null,"abstract":"This paper presents an area-efficient temperature sensor with 1°C resolution based on a successive approximation algorithm. SoC requires several die temperature sensors to be integrated in a chip to manage the performance because die temperature directly affects leakage current level and performance of clock-based digital circuits. However, the size of temperatures sensor restricts the use of sensor in several places in a chip. The proposed area efficient temperature sensor uses only 0.13mm2 in Samsung 45nm CMOS process to obtain 1°C resolution in the range from −15°C to 125°C. For accurate temperature sensing, SAR type algorithm and software-based 2-point calibration method are adopted. After the 2-point calibration, the temperature sensor achieves 1°C resolution with ±2°C accuracy and the power consumption is 360uW in 1.8V.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126645203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 5.6 GHz LC digitally controlled oscillator with high frequency resolution using novel quadruple resolution varactor 一种采用新型四倍分辨率变容管的高频分辨率5.6 GHz LC数字控制振荡器
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682918
Anil Kavala, Deok-Soo Kim, Sungchun Jang, D. Jeong
{"title":"A 5.6 GHz LC digitally controlled oscillator with high frequency resolution using novel quadruple resolution varactor","authors":"Anil Kavala, Deok-Soo Kim, Sungchun Jang, D. Jeong","doi":"10.1109/SOCDC.2010.5682918","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682918","url":null,"abstract":"This paper reports a high resolution LC-based digitally controlled oscillator (DCO) using novel quadruple resolution varactor. Proposed DCO has a high frequency resolution and a wide tuning range of 2.2 GHz with a low phase noise at 5.6 GHz. A process and temperature invariant quadruple resolution varactor is proposed to achieve the finest frequency resolution. The proposed varactor achieves one fourth capacitance of a fine varactor, and therefore DCO achieves a very fine frequency resolution with low phase noise. Also, the diode connected circuit makes the proposed varactor robust from the process and temperature variations. The DCO implemented in 0.13 μm CMOS process operates from 3.4 GHz to 5.6 GHz with a resolution from 260 Hz to 0.93 kHz by consuming a power from 5.5 mW to 3.2 mW, respectively. The designed DCO achieves a low phase-noise of −118 dBc/Hz at 1 MHz offset.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132944823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Hierarchical routing architectures in clustered 2D-mesh Networks-on-Chip 集群二维网格片上网络中的分层路由架构
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682890
M. Winter, Steffen Prusseit, P. F. Gerhard
{"title":"Hierarchical routing architectures in clustered 2D-mesh Networks-on-Chip","authors":"M. Winter, Steffen Prusseit, P. F. Gerhard","doi":"10.1109/SOCDC.2010.5682890","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682890","url":null,"abstract":"The growing size of Multi-Processor Systems-on-Chip (MP-SoC) calls for Networks-on-Chip (NoC) which scale with the increasing number of modules attached to them. Though current, 2D-mesh based NoCs scale linearly with the number of modules attached to them, their performance in terms of achievable throughput under typical traffic scenarios degrades. Clustered, hierarchical 2D-mesh NoCs may provide a solution to this problem by shortening the distance between two modules and adding more bandwidth. But it is merely researched what architectures with which parameters are suitable. In this paper we present and evaluate different realizations of clustered, hierarchical 2D-meshes, analyze their performance via cycle accurate simulations, determine their area consumption and derive recommendations which architecture is a suitable solution to the bandwidth degradation problem.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133368242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Noise reduction communication circuits 降噪通信电路
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682983
A. Michael
{"title":"Noise reduction communication circuits","authors":"A. Michael","doi":"10.1109/SOCDC.2010.5682983","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682983","url":null,"abstract":"The demand for longer battery life and faster speeds for communications circuits coupled with the exponential expansion of wireless communications devices is creating increasingly serious noise problems for communications circuits. Longer battery life means lower power consumption usually obtained by reduced noise margins that can only be achieved by better circuit design, but at least this under the designer's control. Demand for more spectrum by the explosion of wireless devices creates noise sources outside the designer's control that must be dealt with by increasingly clever noise attenuation circuits. This paper will review the state of the art for adaptive filtering as applied to external noise attenuation in communication circuits highlighting the most promising technologies including adaptive heterodyne filters.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130801931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A low noise 65nm 1.2V 7-bit 1GSPS CMOS folding A/D converter with a digital self-calibration technique 具有数字自校准技术的低噪声65nm 1.2V 7位1GSPS CMOS折叠式A/D转换器
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682940
Donggwi Choi, Dasom Kim, Kyuik Cho, Daeyun Kim, Minkyu Song
{"title":"A low noise 65nm 1.2V 7-bit 1GSPS CMOS folding A/D converter with a digital self-calibration technique","authors":"Donggwi Choi, Dasom Kim, Kyuik Cho, Daeyun Kim, Minkyu Song","doi":"10.1109/SOCDC.2010.5682940","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682940","url":null,"abstract":"In this paper, a 65nm 1.2V 7-bit 1GSPS A/D converter with a self-calibration technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2, interpolation rate is 8. An offset self-calibration circuit with a feedback loop and a recursive digital code inspection is described. The offset self-calibration circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW at 1.2V power supply. The measured SNDR is about 38.48dB when the input frequency is 250MHz at 1GHz sampling frequency. The measured SNDR is 3dB higher than the same ADC without any calibration.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133844962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
FiX-compact: A new X-tolerant response compaction scheme for fixed unknown logic values FiX-compact:一种新的x容忍响应压缩方案，用于固定未知逻辑值
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682936
Jaeseok Park, Sungho Kang
{"title":"FiX-compact: A new X-tolerant response compaction scheme for fixed unknown logic values","authors":"Jaeseok Park, Sungho Kang","doi":"10.1109/SOCDC.2010.5682936","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682936","url":null,"abstract":"This paper proposes a new X-tolerant response compaction scheme with a practical assumption where the unknown values are generated on fixed scan chains. The proposed scheme guarantees fault diagnosis and treats simultaneous unknown logic values. In addition, it requires simple compactor structure composed of XOR gates, and it does not need any additional signal from the outside.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131365545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Thermal-aware resource rebinding algorithm for timing optimization in 3D IC designs 三维集成电路设计中用于时序优化的热感知资源重新绑定算法
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682913
P. Lim, Taewhan Kim
{"title":"Thermal-aware resource rebinding algorithm for timing optimization in 3D IC designs","authors":"P. Lim, Taewhan Kim","doi":"10.1109/SOCDC.2010.5682913","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682913","url":null,"abstract":"This work proposes a resource rebinding algorithm in high-level synthesis of 3D IC designs to improve timing under a floorplan information with thermal profile. Our proposed algorithm iteratively extracts a set of operations on critical timing path and updates their bindings to fine-tune the timing variation caused by the irregular temperature distribution. Precisely, the algorithm rebinds operations so that the temperature-induced timing variations should be as low as possible while considering TSV (Through-Silicon Via) cost. Through experimentations using MediaBench designs, it is shown that our thermal-aware rebinding algorithm is able to reduce the design latency by 15% ∼ 20% further over the results by conventional thermal-unaware high-level synthesis.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"343 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131033012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Selectively patterned masks: Beyond structured ASIC 选择性图案掩模:超越结构化ASIC
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682950
Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin
{"title":"Selectively patterned masks: Beyond structured ASIC","authors":"Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin","doi":"10.1109/SOCDC.2010.5682950","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682950","url":null,"abstract":"Conventional structured ASIC still suffers from large delay and area due to the use of homogeneous array of tiles. We propose a new lithography method called selectively patterned masks (SPM), which enables more than one type of tiles to be used in structured ASIC. This structured ASIC using mixture of different tiles relaxes regularity. To assess SPM concept, A new structured ASIC is proposed; tile and routing architecture, and routing algorithm are all addressed. Experiment results using 45-nm technology show that proposed concept can push the limit of structured ASIC closer to traditional ASIC.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129241305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DCT-based scheme to accelerate multimedia search in NAND Flash memories 基于dct的NAND闪存多媒体搜索加速方案
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682972
Shruti Vyas, Aswin Sreedhar, S. Kundu
{"title":"DCT-based scheme to accelerate multimedia search in NAND Flash memories","authors":"Shruti Vyas, Aswin Sreedhar, S. Kundu","doi":"10.1109/SOCDC.2010.5682972","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682972","url":null,"abstract":"NAND Flash memories are gaining popularity due to their high density, robustness, low power consumption and low read times. Searching data in NAND flash memory is fast for small memory sizes but as the memory size increases, searches become painfully slow. With increased user content inclining towards large multimedia such as images, audio and video, there is a need for faster multimedia content searches (MCS). In this paper we develop a hardware based enhancement technique for fast multimedia content searches in NAND Flash memories. The central idea is to compress the multimedia data by applying Discrete Cosine Transform (DCT) and storing selected coefficients as signatures in the spare blocks of the memory. When a multimedia search request comes in, a signature of the search request is computed and only the signature blocks are compared for a match, thus making faster searches. DCT-based compression gives good results for text, audio, image and video files. If a small part of a multimedia data is given as search request, this technique returns all possible matches found in the set of files stored in the flash memory. Applications of this technique can be found in entertainment industry, music libraries, face recognition etc. Simulations are run for memories between size 2Gb to 16Gb. A speed-up of 450X in the search operation is achieved with this technique. The additional hardware has no performance impact on read or sequential writes of memory. The hardware overhead is estimated to be 0.03% of the total memory area.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123423924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low power parallel encoding system for video surveillance applications 用于视频监控的低功耗并行编码系统
2010 International SoC Design Conference Pub Date : 2010-11-01 DOI: 10.1109/SOCDC.2010.5682929
Xin Jin, Kun Ba, S. Goto
{"title":"Low power parallel encoding system for video surveillance applications","authors":"Xin Jin, Kun Ba, S. Goto","doi":"10.1109/SOCDC.2010.5682929","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682929","url":null,"abstract":"In this paper, an encoding system is proposed to further reduce the power consumption in parallel video encoding based on difference detection and Hilbert transform based workload estimation (HTWE). The proposed parallel encoding system provides an average of 40% computational complexity reduction for parallel encoding without objective performance loss. For the multi-core platform with frequency and voltage scalability, up to 78% of power reduction can be achieved.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125324473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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