{"title":"Noise management in highly heterogeneous SoC based integrated circuits","authors":"E. Salman","doi":"10.1109/SOCDC.2010.5682987","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682987","url":null,"abstract":"Noise coupling is one of the most fundamental issues in the design of highly heterogeneous, robust integrated systems. A two-step noise management methodology is proposed in this paper. In the first step, a methodology is described to efficiently analyze noise coupling in large scale circuits while maintaining sufficient accuracy. The second step consists of a methodology to significantly mitigate switching noise. The first step helps determining the required signal isolation and the efficacy of the noise reduction technique proposed in the second step. The two primary noise coupling paths in hybrid systems utilizing three dimensional (3-D) integration technology are also identified.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125456837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"3D TCAD based approach for the evaluation of nanoscale devices during ESD failure","authors":"M. Shrivastava, H. Gossner, M. Baghini, V. Rao","doi":"10.1109/SOCDC.2010.5682919","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682919","url":null,"abstract":"This paper demonstrates a 3D TCAD based approach towards the evaluation and pre-silicon development of nanoscale devices for advanced ESD protection concepts. Impact of various physical models and parameters on the accuracy of predicted ESD figures of merit are discussed. Moreover, various devices options, have been evaluated from 3D TCAD simulations.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124001800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sejin Yoo, Gwangyol Noh, Kwangsoo Kim, G. Ahn, Jun-Seok Lee, Jong-Muk Lee, I. Choi
{"title":"A 1.6V ΔΣ ADC for digital electret microphone","authors":"Sejin Yoo, Gwangyol Noh, Kwangsoo Kim, G. Ahn, Jun-Seok Lee, Jong-Muk Lee, I. Choi","doi":"10.1109/SOCDC.2010.5682915","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682915","url":null,"abstract":"A switched-capacitor delta-sigma analog-to-digital converter (ADC) including preamplifier and bandgap reference for digital electret microphone is presented. It uses quantization noise coupling to achieve third-order noise shaping with only two integrators. The prototype ADC is fabricated in a 0.18μm CMOS process. The single-loop, 1-bit, third-order delta-sigma ADC operates at OSR of 64 provides 70.8dB dynamic range (DR) and 65.7dB peak signal-to-noise ratio (SNR) over a signal bandwidth of 20kHz with 1.6V supply while consuming 1mW power including preamplifier and on-chip reference.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117182376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high-performance concatenated BCH code and its hardware architecture for 100 Gb/s long-haul optical communications","authors":"Kihoon Lee, Hanho Lee","doi":"10.1109/SOCDC.2010.5682880","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682880","url":null,"abstract":"This paper presents a six-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed six-iteration concatenated BCH code structure with a block interleaving methods allows the decoder to achieve 9.19 dB net coding gain performance at 10−15 decoder output bit error rate to compensate for serious transmission quality degradation. Also, the proposed high-speed concatenated BCH decoder architecture was implemented to support 100 Gb/s data processing rate. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s long-haul optical communications.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117229839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interactive partial video decoding for viewing resolution adaptation","authors":"Chen Liu, Xin Jin, T. Zhang, S. Goto","doi":"10.1109/SOCDC.2010.5682925","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682925","url":null,"abstract":"High-definition (HD) and super-high-definition (SHD) videos become more and more popular for various video applications, including video capture and playback on portable devices. Because of the resolution mismatch between HD/SHD video and the low resolution screen of portable devices, the video is fully decoded and then sown-sampled for the display, which causes a waste of both computational power and memory bandwidth. In this paper, a user-defined region of interest (ROI) oriented partial decoding scheme for H.264/AVC is proposed to achieve low-power and good subjective visual quality of decoding/display for viewing resolution adaptation. The proposed partial decoding scheme works basing on the adaptive ROI tracking. The motion-vector (MV) adaptation is adopted for maintaining the visual quality in ROI. The simulation results show that, the displayed partial decoded sequence provides better subjective visual quality, more details, and very small PSNR drop in ROI compare to original one. And the partial decoder achieves about 48.34% decoding time reduction averagely, which means lower computational complexity and power consumption. The proposal is especially useful for displaying HD video on the portable devices in which the battery life is a crucial factor.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124114932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On run time task graph extraction of SoC","authors":"Kunal P. Ganeshpure, S. Kundu","doi":"10.1109/SOCDC.2010.5682892","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682892","url":null,"abstract":"System on Chip (SoC) consists of multiple cores communicating with each other using a communication back plane. The SoC programming model is based on a task graph where a node represents an operation to be scheduled on a core while the edges represent the communication between these operations. Each node and edge is weighted by duration of computation or communication. In a task graph there could be more nodes that can run in parallel than cores. This leads to a scheduling problem. Typically such scheduling is done statically during program development based on estimated execution times. In this paper we propose hardware based dynamic task scheduling driven by real execution times. A key challenge in implementing hardware based task scheduling is runtime discovery of the task graph. It has been observed that most applications have phases because of the presence of loops where only a task graph is executed repeatedly. In this work, we propose to dynamically extract the task graph information in a bus based SoC by adding extra logic to the arbiter which monitors the bus communication and extracts the task graph for the current application phase. The extracted task graph can then be used by the arbiter to adaptively change the priority for bus grant so as to maximize performance. It is seen from our experiments that in most cases it takes less than 100 task graph iterations for our algorithm to extract the application task graph. This is small as compared to millions of task graph iterations in a typical application.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132014345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A sync processor with noise robustness for 3DTV active shutter glasses","authors":"Daejin Park, T. Kim, Chang-Min Kim, Sungho Kwak","doi":"10.1109/SOCDC.2010.5682952","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682952","url":null,"abstract":"A noise robust sync processor chip for 3DTV shutter glasses is proposed and implemented. The existing 3DTV shutter glasses have to receive the sync pulse continuously from the 3DTV to synchronize between two independently-clocked systems. These sync packets are easily interfered by the noise of fluorescent light and the existing TV remote controller signal. Especially the 3DTV users easily suffer from the flicker effect by the synchronization loss. The proposed sync processor adopts the CRC protection for the non-valid sync packet, frame indexing for the valid signal, and newly designed timer to synchronize without any sync signal reception for about one hour to achieve perfect noise robustness. The 3DTV shutter glasses controller including the proposed sync processor is fabricated in 0.18um CMOS technology, has a die size of 2.4mm × 2.3mm.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132199696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xin Wang, Lin Lin, He Tang, Jian Liu, Q. Fang, H Zhao, Albert Z. H. Wang, S. Fan, X. Guan, B. Zhao, Zitao Shi, Yuhua Cheng, B. Qin, Liwu Yang
{"title":"UWB SoC co-design with ESD protection","authors":"Xin Wang, Lin Lin, He Tang, Jian Liu, Q. Fang, H Zhao, Albert Z. H. Wang, S. Fan, X. Guan, B. Zhao, Zitao Shi, Yuhua Cheng, B. Qin, Liwu Yang","doi":"10.1109/SOCDC.2010.5682986","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682986","url":null,"abstract":"This paper discusses critical aspects for co-design of ultra wideband (UWB) system-on-chip (SoC) and on-chip electrostatic discharge (ESD) protection, which are beyond simple data rate and bandwidth considerations. UWB-ESD co-design techniques and experiment results are presented. The designs were implemented in a commercial 0.18μm RFCMOS.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124706776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low power implementation of MDCT/IMDCT for MP3 audio decoder","authors":"Hi-Seok Kim, Sea-Ho Kim, Ki-Seok Chung, T. Han","doi":"10.1109/SOCDC.2010.5682951","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682951","url":null,"abstract":"The MDCT/IMDCT is the basic processing component for digital audio compression. It is also the most computationally intensive operation in audio compression standards. MP3 is still used in the audio standards for audio compression. This paper presents a new and efficient implementation of 12/36-point MDCT/IMDCT architectures for MP3. The proposed architecture utilize Chartered 90nm CMOS technology and optimized for low power applications. Low power libraries and clock gating technique are used for power reduction. Our experimental results show the effectiveness to implementation of MDCT /IMDCT core for MP3","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114612182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel IME instructions and their hardware architecture for ME ASIP","authors":"Hee Kwan Eun, S. Hwang, M. Sunwoo","doi":"10.1109/SOCDC.2010.5682954","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682954","url":null,"abstract":"This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs such as H.264/AVC and MPEG4. With the proposed specific instructions and hardware accelerators, it can handle the processing requirement of High Definition (HD) video. With parallel SAD Processing Elements (PEs) using pattern information, the proposed IME instruction supports not only the full search algorithm but also other fast search algorithms. The gate count is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP with sixteen PEGs runs at 160MHz and can handle 1080p@30 frame in realtime.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116606035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}