Novel IME instructions and their hardware architecture for ME ASIP

Abstract

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs such as H.264/AVC and MPEG4. With the proposed specific instructions and hardware accelerators, it can handle the processing requirement of High Definition (HD) video. With parallel SAD Processing Elements (PEs) using pattern information, the proposed IME instruction supports not only the full search algorithm but also other fast search algorithms. The gate count is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP with sixteen PEGs runs at 160MHz and can handle 1080p@30 frame in realtime.