On run time task graph extraction of SoC

System on Chip (SoC) consists of multiple cores communicating with each other using a communication back plane. The SoC programming model is based on a task graph where a node represents an operation to be scheduled on a core while the edges represent the communication between these operations. Each node and edge is weighted by duration of computation or communication. In a task graph there could be more nodes that can run in parallel than cores. This leads to a scheduling problem. Typically such scheduling is done statically during program development based on estimated execution times. In this paper we propose hardware based dynamic task scheduling driven by real execution times. A key challenge in implementing hardware based task scheduling is runtime discovery of the task graph. It has been observed that most applications have phases because of the presence of loops where only a task graph is executed repeatedly. In this work, we propose to dynamically extract the task graph information in a bus based SoC by adding extra logic to the arbiter which monitors the bus communication and extracts the task graph for the current application phase. The extracted task graph can then be used by the arbiter to adaptively change the priority for bus grant so as to maximize performance. It is seen from our experiments that in most cases it takes less than 100 task graph iterations for our algorithm to extract the application task graph. This is small as compared to millions of task graph iterations in a typical application.