Capacitive interpolated Flash ADC design technique

Abstract

Analog-to-digital converter (ADC) is a key component electronic system. Flash ADC is widely used in high-speed systems. However, practical flash ADC design is very challenging where experience plays a significant role. ADC design involves in many factors at different levels including architecture, circuit, device and technology. This paper reports a quantitative design methodology for capacitive interpolated flash ADCs, which establishes a design matrix that links ADC chip performance with architecture, block circuit, devices and process parameters. Complex relationship among critical ADC specs, such as, sampling speed, interpolation factors, number of stages, preamplifier bandwidth and transistor parasitic effects, etc, are described. An accurate dynamic power analysis technique is depicted. This flash ADC design method was validated using several designs in 90nm and 130nm CMOS technologies.