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Decision diagrams for the design of reversible and quantum circuits 可逆电路和量子电路设计的决策图
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379626
R. Wille, Philipp Niemann, Alwin Zulehner, R. Drechsler
{"title":"Decision diagrams for the design of reversible and quantum circuits","authors":"R. Wille, Philipp Niemann, Alwin Zulehner, R. Drechsler","doi":"10.1109/ISDCS.2018.8379626","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379626","url":null,"abstract":"Reversible circuits found great interest in the past as an alternative computation paradigm which can be beneficial e.g. for encoder circuits, low power design, adiabatic circuits, verification, and much more. Besides that, reversible circuits provide the basis for many components of quantum circuits, which by themselves emerged as a very promising computing technology that, particularly these days, gains more and more relevance. All that led to a steadily increasing demand for methods that efficiently and correctly design such circuits. Decision diagrams play an important role in the design of conventional circuitry. In the meantime, also their benefits for the design of the newly emerging reversible and quantum circuits become evident. In this overview paper, we review and illustrate past work on decision diagrams for such circuits and sketch corresponding design methods relying on them. By this, we demonstrate how broadly decision diagrams can be employed in this area and what benefits they yield for these emerging technologies.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133686913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fabrication and electrical characterization of TiO2NT/RGO/Pd hybrid structure TiO2NT/RGO/Pd杂化结构的制备及电学表征
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379687
S. Ghosal, P. Bhattacharyya
{"title":"Fabrication and electrical characterization of TiO2NT/RGO/Pd hybrid structure","authors":"S. Ghosal, P. Bhattacharyya","doi":"10.1109/ISDCS.2018.8379687","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379687","url":null,"abstract":"In the present work, the room temperature electrical characterization ((a) Current-Voltage (I-V) and (b) Capacitance-Voltage (C-V)) of the ternary hybrid junction based on Pd nanoparticles, Reduced Graphene Oxide (RGO) and TiO2 nanotubes is being reported. The heterojunction was fabricated by growing TiO2 oxide layer on Ti substrate by anodization method. Electrochemically derived TiO2 nanotubes were almost partially covered by transparent RGO layer, on top of which Pd nanoparticles were dispersed randomly. Structural, morphological and optical characterization like XRD, FESEM and PL were carried out in order to investigate the crystallinity, morphological feature and band gap of the grown film. Beside this, low barrier schottky nature and MOS capacitor like feature was confirmed respectively from the current-voltage characteristics (I-V) and capacitance-voltage (C-V) characteristics of the heterojunction of Au/(Pd/RGO/TiO2)/Ti based hybrid device respectively. Calculated the low threshold voltage of the device, as calculated from I-V and C-V plot, makes it useful for high performance and low power operation.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126871340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Driving a Charged Coupled Device (CCD) by microcontroller for LIBS based application 用单片机驱动电荷耦合器件(CCD)实现基于LIBS的应用
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379684
Avijit Mandal, Subhodip Panda, A. Goswami
{"title":"Driving a Charged Coupled Device (CCD) by microcontroller for LIBS based application","authors":"Avijit Mandal, Subhodip Panda, A. Goswami","doi":"10.1109/ISDCS.2018.8379684","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379684","url":null,"abstract":"CCD is one of the important components in digital imaging. In this paper we analyzed the Charged Coupled Device (CCD) which is going to be used in a LASER INDUCED BREAKDOWN SPECTROGRAPHY (LIBS). Here this LIBS instrument is used for getting the knowledge of the soil mineral composition in agricultural purposes. We provide a total android device controlled platform to drive the total system. Now the main impediment in LIBS is that CCD is driven by FPGA. If we want to optimize the cost we must avoid the FPGA. So we drove the CCD is by ARM Microcontroller that is used in ARDUINO due Board. In this paper for the very first time we present a method to drive TCD1201D CCD image sensor with ARM based microcontroller and also incorporated method of control by android device. Now to drive that CCD we need 6 clock signals (SH, ICG, PHI1, PHI2, RS, BT) that will give the output OS & DOS. We gave the 2 outputs to a difference amplifier whose output is now fed to the OP484 for amplification. The output of the difference amplifier is then given to one analog channel. From that channel the CCD OUTPUT is analyzed. This CCD OUTPUT is going to an ANDROID device by HC-05 BLUETOOTH module.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115432540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of ternary logic circuits using CNTFET 利用CNTFET设计三元逻辑电路
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379661
Debaprasad Das, A. Banerjee, Vikash Prasad
{"title":"Design of ternary logic circuits using CNTFET","authors":"Debaprasad Das, A. Banerjee, Vikash Prasad","doi":"10.1109/ISDCS.2018.8379661","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379661","url":null,"abstract":"The work in this paper presents the design of ternary logic circuits using MOSFET-like carbon nanotube field effect transistor (CNTFET). The ternary logic is one of multivalued logic circuits which is the best substitute for traditional binary logic because of its low power consumption and low power delay product (PDP) resulting from reduced complexity of interconnects and chip area. CNTFET is preferred over Si-MOSFET for logic design due to its excellent thermal, mechanical and electrical properties. In addition, CNTFETs have the capability of having the desired threshold voltage by changing the diameters of the nanotubes, which make them a very suitable device for voltage mode multiple threshold circuit design. In this paper, we have shown how the ternary logic circuits can be efficiently designed using CNTFETs. The chirality of the carbon nanotube (CNT) is varied to vary the diameter of the CNT and hence the threshold voltage of the CNTFET. We have designed a ternary multiplier using CNTFETs at 32nm technology node. Our design shows ∼ 2000 × less delay and 104× less power as compared to that of existing designs.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116824718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Effect Of body bias and temperature on snapback for a SOI-LDMOS transistor 体偏置和温度对SOI-LDMOS晶体管回跳的影响
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379666
Jagamohan Sahoo, R. Mahapatra, A. Bhattacharyya
{"title":"Effect Of body bias and temperature on snapback for a SOI-LDMOS transistor","authors":"Jagamohan Sahoo, R. Mahapatra, A. Bhattacharyya","doi":"10.1109/ISDCS.2018.8379666","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379666","url":null,"abstract":"In this paper we have addressed the effect of body bias (both forward and reverse bias) and temperature on snapback voltage in a Silicon On Insulator Lateral Diffused MOS (SOI-LDMOS) transistor for the first time. Controlled simulation experiments have been carried out on a representative LDMOS structure to develop physical insight regarding the effect of body bias on the device characteristics. For temperature effect, only the temperature dependence of IDS-VDS characteristics has been presented. The simulation results are expected to be useful for developing analytical model capable of including bias and temperature dependences and validating prevailing models. The forward body bias assists the parasitic bipolar transistor to turn on in lower drain to source voltage and reduces snapback voltage from ∼ 50V to ∼20V for the dimension and parameters given in Table 1. However, the snapback voltage is increased slowly in reverse body bias. Depending on application, optimum snapback voltage may be tuned by varying the body bias. The snapback voltage hardly changed with the temperature variation from 250C to 1250C.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1999 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128250210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design, analysis, fabrication and testing of a silicon carbide-based high frequency ZCS buck converter with over current protection 基于碳化硅的高频ZCS过流保护降压变换器的设计、分析、制造和测试
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379651
Saikat Dey, Abhishek Kar, M. Sengupta
{"title":"Design, analysis, fabrication and testing of a silicon carbide-based high frequency ZCS buck converter with over current protection","authors":"Saikat Dey, Abhishek Kar, M. Sengupta","doi":"10.1109/ISDCS.2018.8379651","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379651","url":null,"abstract":"Higher switching frequencies in power electronic converters result in reduction of size of the passive elements such as capacitors, inductors and transformers which lead to compact size, weight, and the increased power density of the converters at the cost of increased switching losses. The remedy for higher switching losses is the use of soft switching techniques like Zero-Current-switching (ZCS). Silicon Carbide (SiC) MOSFETs are now-a-days used in switched converters at very high frequencies for their known advantages. This paper presents a ZCS strategy-based buck converter, operating at 92kHz. Performance analysis and simulation of the converter has been done off-line using SEQUEL and other standard packages. Thereafter, a laboratory prototype has been fabricated and tested. The SiC MOSFET is driven by a gate driver card (tested upto 2 MHz), developed in the laboratory. Over current protection is also implemented. The experimental and simulated results are found to be in excellent agreement.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122700504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Performance modeling of intercalation doped graphene-nanoribbon interconnects 嵌入掺杂石墨烯-纳米带互连的性能建模
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379685
Subhajit Das, Debaprasad Das, H. Rahaman
{"title":"Performance modeling of intercalation doped graphene-nanoribbon interconnects","authors":"Subhajit Das, Debaprasad Das, H. Rahaman","doi":"10.1109/ISDCS.2018.8379685","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379685","url":null,"abstract":"In this work, we have presented the temperature dependent equivalent single conductor (ESC) model and performance analysis of undoped and doped multilayer graphene nanoribbon (MLGNR) interconnects. The common resistive model of both top-contact and side-contact multilayer GNR interconnects has been demonstrated using multi-conductor based methodology. The propagation delay of pristine (undoped), Arsenic pentafluoride (AsF5), Ferric chloride (FeCl3) and Lithium (Li) intercalation doped MLGNR interconnect is investigated for different temperature and different interconnect length at 16nm technology node. The results show a considerable rise of delay of MLGNR interconnects with the rise of temperature. It is found that AsF5-, FeCl3- and Li-intercalated top-contact MLGNR interconnects show superior resistive performance than that of its pristine counterpart at higher temperature. Li-intercalated TC-MLGNR has been found to be the fastest among all types of MLGNR interconnects as well as conventional Cu over the temperature range from 150K to 450K.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125693050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Performance investigation of Negative Capacitance Germanium Double Gate-pFET (NCGe-DG-pFET) for improved analog applications 用于改进模拟应用的负电容锗双栅极pfet (NCGe-DG-pFET)性能研究
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379686
Monika Bansal, H. Kaur
{"title":"Performance investigation of Negative Capacitance Germanium Double Gate-pFET (NCGe-DG-pFET) for improved analog applications","authors":"Monika Bansal, H. Kaur","doi":"10.1109/ISDCS.2018.8379686","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379686","url":null,"abstract":"In the present work, a drain current model for novel device Negative Capacitance Germanium Double Gate p-type Field Effect Transistor (NCGe-DG-pFET) has been proposed by using Poisson's equation and Landau-Khalatnikov equation. In order to assess the efficacy of proposed device for sharp switching characteristics and low voltage/low power analog applications, electrical characteristics of the proposed device such as gate capacitance, subthreshold swing and drain current have been obtained and studied for a wide range of device parameters and bias conditions. By comparing the characteristics of the proposed device with conventional Germanium Double Gate p-type Field Effect Transistor (Ge-DG-pFET), it is demonstrated that proposed device exhibits enhanced gate controllability, improved current drivability and sub-60 mV/dec subthreshold swing (SS) so it is suitable for analog applications.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123360946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Width optimization of intercalation doped multilayer graphene nanoribbon interconnects 嵌入掺杂多层石墨烯纳米带互连的宽度优化
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379653
B. Kumari, Manodipan Sahoo
{"title":"Width optimization of intercalation doped multilayer graphene nanoribbon interconnects","authors":"B. Kumari, Manodipan Sahoo","doi":"10.1109/ISDCS.2018.8379653","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379653","url":null,"abstract":"In this work, we have optimized width of Multilayer Graphene Nanoribbon (MLGNR) interconnects by minimizing the crosstalk delay and noise parameters for intermediate and global level interconnects at 11 nm technology node by utilizing the ABCD parameter based model. It is observed that perfectly and nearly specular (i.e P=1 and 0.8 respectively) MLGNR interconnects having width ranging from 10 to 20 nm for intermediate level and from 50 to 100 nm for global level have lesser crosstalk delay and are more immune to noise. When compared to Cu, perfectly and nearly specular MLGNRs outperform Cu in terms of delay for both intermediate and global level but only global level interconnects have better immunity to noise than Cu.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124509500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effective power system operation by using supply-demand manager 利用供需管理器有效地运行电力系统
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379675
Y. Sasaki, Zoka Yoshifumi, N. Yorino
{"title":"Effective power system operation by using supply-demand manager","authors":"Y. Sasaki, Zoka Yoshifumi, N. Yorino","doi":"10.1109/ISDCS.2018.8379675","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379675","url":null,"abstract":"Future perspective of the dramatic increase in renewable energy sources (RESs), such as photovoltaic power generations (PVs), may lead to severe problems related to power system operation such as load dispatch. Other important aspect is the reduction of controllable resources yielding concerns about the reliability issues of such sources. This paper focuses on a new method and technique for mitigating the irregularity associated with RES. In this paper, we propose a new generation schedule method to realize real-time dynamic economic load dispatch (RDED) as an efficient solution for real-time management with uncertainties of PVs, over the limited resources of a power system.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129634071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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