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Test Data Compression with Partial LFSR-Reseeding 部分lfsr - re播测试数据压缩
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.105
Yu-Hsuan Fu, Sying-Jyan Wang
{"title":"Test Data Compression with Partial LFSR-Reseeding","authors":"Yu-Hsuan Fu, Sying-Jyan Wang","doi":"10.1109/ATS.2005.105","DOIUrl":"https://doi.org/10.1109/ATS.2005.105","url":null,"abstract":"The large amount of test data becomes a serious problem in SOC testing. In this paper, we propose a method to improve the LFSR reseeding based compression scheme. This method rearranges a given set of test data by merging and partitioning test cubes so that they can be decompressed with a fixed-length LFSR. The compression is done by eliminating repeated patterns in consecutive seeds. A singlepolynomial LFSR is used, so that the decompression process is simple and fast. Besides, it does not need an on-chip decoder. The compression method is very efficient, as experimental results show that it reduces 23.6% of stored data and 34.8% of transferred data compared with the previous methods.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133974917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Class of Linear Space Compactors for Enhanced Diagnostic 一类用于增强诊断的线性空间压实器
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.7
T. Clouqueur, H. Fujiwara, K. Saluja
{"title":"A Class of Linear Space Compactors for Enhanced Diagnostic","authors":"T. Clouqueur, H. Fujiwara, K. Saluja","doi":"10.1109/ATS.2005.7","DOIUrl":"https://doi.org/10.1109/ATS.2005.7","url":null,"abstract":"Testing of VLSI circuits is challenged by the increasing volume of test data that adds constraints on tester memory and impacts test application time substantially. Space compactors are commonly used to reduce the test volume by one or two orders of magnitude. However, such level of compaction reduces the quality of the diagnostic of faults because it is difficult to identify the locations of errors in the compacted response. In this paper, we introduce a design of space compactors that can be used in pass/fail mode as well as in diagnostic mode with enhanced performance by trading off compaction ratio for diagnostic ability. We analyze the properties of the compactors and evaluate their performance through simulations","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130955881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Delay Defect Characterization Using Low Voltage Test 用低电压试验表征延迟缺陷
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.45
Haihua Yan, A. Singh, Gefu Xu
{"title":"Delay Defect Characterization Using Low Voltage Test","authors":"Haihua Yan, A. Singh, Gefu Xu","doi":"10.1109/ATS.2005.45","DOIUrl":"https://doi.org/10.1109/ATS.2005.45","url":null,"abstract":"For nanometer designs, many subtle defects lead to excessive delays in signal paths that cause reliability concerns. Traditional test-based diagnosis methods can only identify the failing nodes without the capability to tell the defect nature behind the observed delay faults. This differentiation is important for gathering accurate defect statistics for process improvement during yield ramp-up. In this paper we presented an effective delay defect analysis methodology that can quickly categorize the delay defects into either transistor related defects or resistive interconnect defects. The new delay defect/failure characterization method is based on low voltage test and delay defect detection in slack interval (DDSI) method. Experimental results were presented to validate the effectiveness of the new method. Practical considerations were also addressed for adoption of the methodology.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123677125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Partial Gating Optimization for Power Reduction During Test Application 在测试应用过程中降低功率的部分门控优化
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.87
Mohammed ElShoukry, M. Tehranipoor, C. Ravikumar
{"title":"Partial Gating Optimization for Power Reduction During Test Application","authors":"Mohammed ElShoukry, M. Tehranipoor, C. Ravikumar","doi":"10.1109/ATS.2005.87","DOIUrl":"https://doi.org/10.1109/ATS.2005.87","url":null,"abstract":"Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to block transitions from propagating from the outputs of scan cells through combinational logic. In order to accomplish this, some authors have proposed the setting of primary inputs to appropriate values or adding extra gates at the outputs of scan cells. In this paper, we point out the limitations of such full gating technique. We propose an alternate solution where a partial set of scan cells is gated. The subset of scan cells is selected to give maximum reduction in test power within a given area constraint. An alternate formulation of the problem is to treat maximum permitted test power and area overhead as constraints and achieve a test power that is within these limits using the fewest number of gated scan cells, thereby leading to least impact in area overhead. Our problem formulation also comprehends performance constraints and prevents the inclusion of gating points on critical paths. The area overhead is predictable and closely corresponds to the average power reduction.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126777808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Practical Aspects of Delay Testing for Nanometer Chips 纳米芯片延迟测试的实际应用
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.89
V. Chickermane, B. Keller, K. McCauley, A. Uzzaman
{"title":"Practical Aspects of Delay Testing for Nanometer Chips","authors":"V. Chickermane, B. Keller, K. McCauley, A. Uzzaman","doi":"10.1109/ATS.2005.89","DOIUrl":"https://doi.org/10.1109/ATS.2005.89","url":null,"abstract":"As SoC feature sizes are moving down to the nanometer range there is an increasing need to develop high quality, cost-effective and sensitive tests for nanometer devices. Many of the newer defects like resistive vias and bridges exhibit defective timing behavior, and require the usage of the transition fault model and sophisticated control of the launch-to-capture timings to the equivalent of system speeds.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114451801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synthesis of Testable Finite State Machine Through Decomposition 可测试有限状态机的分解综合
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.102
B. Sikdar, Arijit Sarkar, Samir Roy, D. K. Das
{"title":"Synthesis of Testable Finite State Machine Through Decomposition","authors":"B. Sikdar, Arijit Sarkar, Samir Roy, D. K. Das","doi":"10.1109/ATS.2005.102","DOIUrl":"https://doi.org/10.1109/ATS.2005.102","url":null,"abstract":"This paper reports an efficient state encoding scheme for synthesis of large FSMs with enhanced BIST quality. A metric, referred to as degree-of-freedom (DOF) (Roy et al., 2002) in FSM states has been employed to quantify the BIST quality. Analysis of DOF enables efficient encoding of FSM states and gives solution to the problem of handling unreachable/hard-to-exit/hard-to-reach state codes of an FSM. The synthesis of a large FSM is realized through decomposition. DOF analysis for the individual component sub-FSM states is done to reduce the complexity of synthesis. A scheme is proposed for encoding the sub-FSM states that significantly improves testability of the synthesized resultant FSM, displaying the terminal behavior as the original FSM","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130927865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A State Machine for Detecting C/C++ Memory Faults 一种检测C/ c++内存故障的状态机
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.15
Guangyan Huang, Guangmei Zhang, Xiaowei Li, Yunzhan Gong
{"title":"A State Machine for Detecting C/C++ Memory Faults","authors":"Guangyan Huang, Guangmei Zhang, Xiaowei Li, Yunzhan Gong","doi":"10.1109/ATS.2005.15","DOIUrl":"https://doi.org/10.1109/ATS.2005.15","url":null,"abstract":"Memory faults are major forms of software bugs that severely threaten system availability and security in C/C++ program. Many tools and techniques are available to check memory faults, but few provide systematic full-scale research and quantitative analysis. Furthermore, most of them produce high noise ratio of warning messages that require many human hours to review and eliminate false-positive alarms. And thus, they cannot locate the root causes of memory faults precisely. This paper provides an innovative state machine to check memory faults, which has three main contributions. Firstly, five concise formulas describing memory faults are given to make the mechanism of the state machine simple and flexible. Secondly, the state machine has the ability to locate the cause roots of the memory faults. Finally, a case study applying to an embedded software, which is written in 50 thousand lines of C codes, shows it can provide useful data to evaluate the reliability and quality of software","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122680328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects 任意互连中串扰效应边界的计算方法
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.11
Wichian Sirisaengtaksin, S. Gupta
{"title":"A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects","authors":"Wichian Sirisaengtaksin, S. Gupta","doi":"10.1109/ATS.2005.11","DOIUrl":"https://doi.org/10.1109/ATS.2005.11","url":null,"abstract":"In this paper, we present a methodology that uses the moments of a generic crosstalk pulse signal to derive upper bounds on the amplitude of crosstalk pulse in arbitrary interconnects. We apply the proposed methodology to identify vectors that invoke crosstalk pulses with severities less than thresholds at which circuit may malfunction. These vectors are then excluded from the test set, reducing test application time. Case studies that consider interconnects with rich topologies, including cases where we consider process variations or treat lengths of nets as variables, clearly demonstrate the effectiveness of the methodology.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125004039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
T1: Design for Manufacturability T1:可制造性设计
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.103
Y. Zorian, J. Carballo
{"title":"T1: Design for Manufacturability","authors":"Y. Zorian, J. Carballo","doi":"10.1109/ATS.2005.103","DOIUrl":"https://doi.org/10.1109/ATS.2005.103","url":null,"abstract":"In addition to designing the functionality, today’s SOC necessitates designing for manufacturability, yield and reliability. Such requirements are fundamentally transforming the current SoC design methodology techniques for enhancing manufacturability, yield and reliability or \"DFX\" to include yield enhancement techniques, resolution enhancement techniques, new or restricted design rules, variability-aware design, and the addition of a special family of embedded IP blocks, called infrastructure IP blocks. The latter blocks are meant to ensure manufacturability of the SoC and to achieve adequate levels of yield and reliability. The infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This tutorial analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of the above DFX techniques. Then, it concentrates on several examples of each of these techniques.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123162719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Defect-Oriented Test for Ultra-Low DPM 超低DPM缺陷导向测试
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.44
V. Iyengar, P. Nigh
{"title":"Defect-Oriented Test for Ultra-Low DPM","authors":"V. Iyengar, P. Nigh","doi":"10.1109/ATS.2005.44","DOIUrl":"https://doi.org/10.1109/ATS.2005.44","url":null,"abstract":"Business demand for ultra-low defects-permillion (DPM) levels and the emergence of subtle defects that often manifest as functional errors only in the presence of certain specific environmental conditions such as crosstalk, have led to a critical need for intelligent, adaptive, and targeted defectoriented test. The classical model of test, in which integrated circuits (ICs) are subjected to a blanket suite of stuck-fault, transition and Iddq test patterns generated without consideration to layout and chip-to-chip differences are now insufficient to bring DPM levels for cutting-edge ICs down to the requisite 10-100 range demanded by qualityconscious customers.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124421514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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