14th Asian Test Symposium (ATS'05)最新文献

{"title":"Pseudo-Parity Testing with Testable Design","authors":"Shiyi Xu","doi":"10.1109/ATS.2005.92","DOIUrl":"https://doi.org/10.1109/ATS.2005.92","url":null,"abstract":"Traditionally, parity testing is one of the exhaustive testing techniques, which needs applying all possible input combinations without need of knowing the implementation of the circuits under test. The way seems to be less interesting to the test engineers in the past days, mainly due to the reasons of its low efficiency and time-consuming, which became a barrier as the number of input lines gets growing. However, in this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing: The main idea of this work is just to change an exhaustive parity testing into a non-exhaustive one, referring to as pseudo-parity, and then followed by a pseudo-parity testable design to help realize the new way of pseudo-parity testing. The technique of pseudo-parity testing presented in this paper can now be used in testing for a large scale of combinational circuit. Experiment results are given to show its facility and usefulness","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126296817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design for Testability: The Path to Deep Submicron","authors":"T. Williams","doi":"10.1109/ATS.2005.48","DOIUrl":"https://doi.org/10.1109/ATS.2005.48","url":null,"abstract":"Design has never been simple, but at 130 nm and below, and definitely at 90 nm, it is becoming increasingly difficult. Process and lithography issues continue to drive our advance to new technology nodes. Due to the effects of scaling, defect mechanisms are no longer easily identified with single \"stuck at\" fault models but rather are demanding far more complex and challenging solutions. For example, shorts are now being extracted from the physical layout of a design, with special tests being created to detect them. But this is just the beginning; delay testing of all transition faults is now a new objective of design for testability (DFT). New demands are being made on design to not only create the correct function and help with testing but also to help yield ramp-up. The areas of design for manufacturing (DFM) and design for yield (DFY) are now also talking hold as new requirements for design. Manufacturing and test are beginning to develop an even stronger relationship due to the close interconnection between yield ramp-up and diagnostics, which are supported by DFT structures included in the design","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132395786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Scan Matrix Design for Low Power Scan-Based Test","authors":"Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen","doi":"10.1109/ATS.2005.14","DOIUrl":"https://doi.org/10.1109/ATS.2005.14","url":null,"abstract":"For the scan design, the circuit under test (CUT) in the test mode usually has larger switching activity than in the function mode, causing excessive power dissipation. In this paper, we propose a new Scan Matrix (SM) architecture for the scan-based design to achieve low power testing. The scan flip-flops are connected in a matrix style for test and its addressing is controlled by two ring generators during pattern scanning in. Unlike the traditional scan, for which scan-in data need to pass through a long path and many scan flip-flops switch simultaneously, the proposed approach dynamically forms a low-power scan path to reduce test energy and peak power during shift significantly. The architecture is scalable for large designs and has minimal circuit performance penalty. Experimental results show that, for some larger designs, nearly 99% power savings have been achieved.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128083925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Power Test Compression Technique for Designs with Multiple Scan Chain","authors":"Youhua Shi, N. Togawa, M. Yanagisawa, T. Ohtsuki, S. Kimura","doi":"10.1109/ATS.2005.76","DOIUrl":"https://doi.org/10.1109/ATS.2005.76","url":null,"abstract":"This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with a pre-computed test cube set and fill the don’t-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS’89 benchmarks show the efficiency of the proposed technique.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133316885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-robust Test Generation for Crosstalk-Induced Delay Faults","authors":"Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li","doi":"10.1109/ATS.2005.81","DOIUrl":"https://doi.org/10.1109/ATS.2005.81","url":null,"abstract":"Crosstalk issues in deep sub-micron (DSM) cause severe design validation and test problems. This paper addresses the problems of delay test considering crosstalkinduced effects, and proposes a non-robust delay test generation method based on single precise crosstalkinduced path delay fault (S-PCPDF) model. With some necessary static timing analysis, the target crosstalkinduced delay fault set was reduced. And the delay test generation for crosstalk-induced delay faults can be implemented by few alterations of non-robust path delay test generation algorithms whereas the timing information is only considered during the selection of target faults. Experimental results on ISCAS’89 and ITC’99 benchmark circuits showed that the proposed method does efficiently for circuits of reasonable sizes, and the CPU time is acceptable.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123673465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Constraint Extraction for Template-Based Processor Self-Test Generation","authors":"K. Kambe, M. Inoue, H. Fujiwara, T. Iwagaki","doi":"10.1109/ATS.2005.52","DOIUrl":"https://doi.org/10.1109/ATS.2005.52","url":null,"abstract":"This paper presents efficient method to extract constraints from a test program template and synthesize a test program using constraint circuits. A test program template is an instruction sequence with unspecified operands, and represents paths for justification of test patterns and observation of test responses for a module under test (MUT). The constraint circuit represents a relation between operand values and inputs/output of the MUT, therefore it enables to obtain operand values using a standard automatic test pattern generator. Experimental results show that the proposed method generates accurate and compact constraint circuits, and we obtain high fault efficiency.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124489333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability","authors":"Swaroop Ghosh, S. Bhunia, K. Roy","doi":"10.1109/ATS.2005.98","DOIUrl":"https://doi.org/10.1109/ATS.2005.98","url":null,"abstract":"Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confidence. In this paper, we analyze the testability in a new style of logic design based on Shannon’s decomposition and supply gating. We observe that tree structure of a logic circuit due to Shannon’s decomposition makes it intrinsically more testable than conventionally synthesized circuit, while at the same time entailing an improvement in active power. We have analyzed three different aspects of testability of a circuit: a) IDDQ test sensitivity b) test power during scan-based testing, and c) test length (for both ATPG-generated deterministic and random patterns). Simulation results on a set of MCNC benchmarks show promising results on all the above aspects. We have also demonstrated that the new logic structure can improve parametric yield of a circuit under process variations when considering a bound on circuit leakage.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124756385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Practices in Testing of Mixed-Signal and RF SoCs","authors":"S. Abdennadher, S. Shaikh","doi":"10.1109/ATS.2005.90","DOIUrl":"https://doi.org/10.1109/ATS.2005.90","url":null,"abstract":"The presentation includes an overview of challenges in testing analog, mixed signal, and RF SoCs, and presents alternative solutions to ATE functional testing for products that are suitable for high volume manufacturing. This talk presents a different level of granularity within mixed signal SoC testing by abstracting the systems in terms of product types, specifications, interfaces, or building blocks. This way, the final testing of the SoC becomes an aggregation of the test techniques targeted for particular product types, interfaces, and building blocks incorporated in the system. Several industrial examples of production testing of mixed-signal and RF devices are presented in this talk","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122067214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A BIST Scheme Based on Selecting State Generation of Folding Counters","authors":"Huaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang","doi":"10.1109/ATS.2005.6","DOIUrl":"https://doi.org/10.1109/ATS.2005.6","url":null,"abstract":"In this paper, a BIST scheme based on selecting state generation of folding counters is presented. LFSR is used to encode the seeds of the folding counters, where folding distances (or indexes) are stored to control deterministic test patterns generation, so that the generated test set is completely equal to the original test set. This scheme solves compression of the deterministic test set and overcomes overlapping and redundancy of test patterns produced by the different seeds. Experimental results prove that it not only achieves higher test data compression ratio, but also efficiently reduces test application time, and that the average test application time is only four percent of that of the same type scheme.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122089209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Emerging Techniques for Test Data Compression","authors":"K. J. Balakrishnan","doi":"10.1109/ATS.2005.57","DOIUrl":"https://doi.org/10.1109/ATS.2005.57","url":null,"abstract":"Increasing test costs has been one of the disadvantageous consequences of technology scaling especially in deep sub-micron designs. The amount of test data required to achieve good test quality has increased tremendously due to the increasing complexity of devices as well as the need to test for newer defect mechanisms that are becoming predominant in smaller device geometries. This has led to the development and deployment of new design-for-test (DFT) technologies to mitigate the problem. Test data compression has been at the forefront of solutions to reduce test costs through reduction in tester storage and test application time. In addition, it has the advantage of needing minimal changes to traditional design flow. The popularity and wide adoption of test data compression can be gauged by the fact that almost all EDA vendors now include test compression with their test solutions. Most test data compression techniques have concentrated on scan test vectors since the bulk of the increase in test data is due to scan vectors, including both stuck-at and delay tests. The test data of scan vectors consist of two parts - the test input or stimulus which is loaded into the scan chains and the test response which is captured at the scan cells after the capture cycle and unloaded through the scan chains for comparison with the correct response. The compression of both these parts present different challenges and hence require separate schemes. The input compression should be loss-less (to avoid reduction in fault coverage) while the response compression is complicated by the presence of unknown values (X's) that are captured in the scan cells. This presentation first briefly summarizes current test data compression techniques. Most of the commercial tools for test data compression utilize on-chip circuits for decompression that belong to the category of linear decompressors. We discuss the limitations of current schemes and look at future challenges. Subsequently, we talk about emerging techniques that seek to overcome these challenges. Several techniques have been developed at NEC Labs for both input test data compression and output (response) compaction. XWRC (Wang et al., 2005) is an externally loaded weighted random pattern compression scheme that combines weighted random pattern testing and LFSR reseeding to achieve very high input compression. PIDISC (Balakrishnan et al., 2006) is a pattern and design independent seed compression scheme to further compress the seeds of LFSR in reseeding based compression schemes. On the output side, a novel compactor to handle test responses with unknown values has been developed (Chao et al., 2005). Response Shaper (2005) is a technique to eliminate the reduction in fault coverage in spatial response compaction due to error masking caused by the appearance of unknown values and even errors. XBlock (Wang et al., 2006) is an efficient LFSR reseeding based technique to block unknown values for temporal compactors","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"23 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120849864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}