Pseudo-Parity Testing with Testable Design

Abstract

Traditionally, parity testing is one of the exhaustive testing techniques, which needs applying all possible input combinations without need of knowing the implementation of the circuits under test. The way seems to be less interesting to the test engineers in the past days, mainly due to the reasons of its low efficiency and time-consuming, which became a barrier as the number of input lines gets growing. However, in this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing: The main idea of this work is just to change an exhaustive parity testing into a non-exhaustive one, referring to as pseudo-parity, and then followed by a pseudo-parity testable design to help realize the new way of pseudo-parity testing. The technique of pseudo-parity testing presented in this paper can now be used in testing for a large scale of combinational circuit. Experiment results are given to show its facility and usefulness