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High Level Test Generation / SW based Embedded Test 高级测试生成/基于软件的嵌入式测试
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.64
Praveen Parvathala
{"title":"High Level Test Generation / SW based Embedded Test","authors":"Praveen Parvathala","doi":"10.1109/ATS.2005.64","DOIUrl":"https://doi.org/10.1109/ATS.2005.64","url":null,"abstract":"As device geometries scale, product complexity has increased with more and more functionality embedded into integrated chips in recent times. In the processor domain, multiple cores with associated glue logic and cache all on a single die are becoming more and more popular. At the same time, product frequencies have gone up and the need to test for delay defects and marginal circuits is rising continually. This is exacerbated in recent times with the focus on lowpower design. While there has been a lot of progress in scan based delay test, the reliance on functional tests has continued. The biggest concern with scan test effectiveness is related to screening small delay defects. Gross delay defects can be tested using a good set of scan transition fault tests (scan AC tests). However questions remain with respect to the effectiveness of scan tests to screen small delay defects and also to test marginality related failures: for example, speed failures caused by issues like cross-capacitance, power droop etc. Functional tests are being used today for getting the last few DPM to reach quality goals. The reliance on functional tests is higher in products that push the process/design envelope to reach performance/power goals.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121151261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Selection of Paths for Delay Testing 延迟测试路径的选择
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.97
I-De Huang, S. Gupta
{"title":"Selection of Paths for Delay Testing","authors":"I-De Huang, S. Gupta","doi":"10.1109/ATS.2005.97","DOIUrl":"https://doi.org/10.1109/ATS.2005.97","url":null,"abstract":"In this paper, we propose a new approach to efficiently identify paths for delay testing. We use a realistic delay model and several new concepts (timing threshold, settling times [14], and timing blocking line) and algorithms, to identify a set of paths that is guaranteed to include all paths that may potentially cause a timing error if the accumulated values of additional delays along circuit paths is upper bounded by a desired limit, ... The first phase of the proposed approach identifies a small subset of all possible paths in the circuit for further analysis. Since this phase only requires breadth-first static timing analysis (forward and backward), its complexity is independent of the number of paths in the circuit as well as the number of all possible two-vector sequences that may be applied to the circuit. We then use new conditions for functional sensitization that help identify paths that may be functionally sensitizable and have the potential of causing timing errors if accumulated values of additional delays along any path is upper bounded by ... The results show that without any search, the proposed approach identifies a near minimal number of paths at low complexity.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"501 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116196473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
The Ultimate Chase 终极追逐
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.107
P. Krishnamurthy
{"title":"The Ultimate Chase","authors":"P. Krishnamurthy","doi":"10.1109/ATS.2005.107","DOIUrl":"https://doi.org/10.1109/ATS.2005.107","url":null,"abstract":"Defects - they come in various shapes and sizes; they make the difference between good and bad; they make us sweat and swear. Catching them all has remained a challenge and will continue to be, for years to come.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127516776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions 使用触发器子集启动转换改进延迟故障覆盖率
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.68
Narendra Devta-Prasanna, S. Reddy, A. Gunda, P. Krishnamurthy, I. Pomeranz
{"title":"Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions","authors":"Narendra Devta-Prasanna, S. Reddy, A. Gunda, P. Krishnamurthy, I. Pomeranz","doi":"10.1109/ATS.2005.68","DOIUrl":"https://doi.org/10.1109/ATS.2005.68","url":null,"abstract":"We describe a novel method to partition flip-flops in scan chains into disjoint groups of flip-flops that are to be driven by independent scan enable signals to achieve higher delay fault coverage. The proposed method to partition flip-flops is motivated by our recent work which demonstrated that driving subsets of flip-flops by independent scan enable signals to launch signal transitions will lead to higher delay fault coverage by broadside tests. As in broadside test none of the scan enable signals need to switch at-speed. Experimental results for delay fault coverage improvement on larger ISCAS-89 benchmark and industrial circuits are presented","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124424334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Chip Identification using the Characteristic Dispersion of Transistor 利用晶体管特性色散的芯片识别
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.35
J. Hirase, T. Furukawa
{"title":"Chip Identification using the Characteristic Dispersion of Transistor","authors":"J. Hirase, T. Furukawa","doi":"10.1109/ATS.2005.35","DOIUrl":"https://doi.org/10.1109/ATS.2005.35","url":null,"abstract":"With the miniaturization of the diffusion process and the emergence of new defects and new fault models, quality guarantee is becoming increasingly difficult. Research on chip ID (Identification) aiming at improving traceability is therefore actively pursued. This paper will discuss the properties of a method making use of the characteristic dispersion of transistor. We will show that our characteristic reasoning and corroborative results thoroughly coincide.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"12 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132192500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach 用电模拟与分析方法研究DRAM故障行为
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.71
Z. Al-Ars, S. Hamdioui, J. Vollrath
{"title":"Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach","authors":"Z. Al-Ars, S. Hamdioui, J. Vollrath","doi":"10.1109/ATS.2005.71","DOIUrl":"https://doi.org/10.1109/ATS.2005.71","url":null,"abstract":"Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modifies the faulty behavior of the memory. This paper introduces an analytical (equation-based) method to give a rough analysis of the faulty behavior of cell opens in the memory, that simplifies the understanding and identifies the major factors responsible for the faulty behavior. Having these factors makes it easier to optimize the circuit and allows extrapolation of the behavior of future technologies. The paper also compares the results of the analytical approach with those from the simulation-based analysis and discusses the advantages and disadvantages of both","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130258666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture 基于测试响应和测试向量重叠的全扫描测试架构测试成本降低方法
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.17
T. Shinogi, H. Yamada, T. Hayashi, S. Tsuruoka, T. Yoshikawa
{"title":"A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture","authors":"T. Shinogi, H. Yamada, T. Hayashi, S. Tsuruoka, T. Yoshikawa","doi":"10.1109/ATS.2005.17","DOIUrl":"https://doi.org/10.1109/ATS.2005.17","url":null,"abstract":"To reduce the test application time and the test data volume in full-scan testing, various methods are proposed which utilize some additional built-in circuits dedicated for testing. In contrast, a previous method, called Reduced Scan Shift, does not utilize any additional built-in hardware. However, the method relies on scan chain flip-flop reordering, which is not always applicable. In this paper, we propose a test data sequence generation method for Reduced Scan Shift without scan chain flip-flop reordering. Our method fully utilizes justification technique and don't-care bits in test vectors.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133788869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size 渐进式随机存取扫描的状态重用测试生成:测试功率、应用时间和数据大小的解决方案
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.101
D. Baik, K. Saluja
{"title":"State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size","authors":"D. Baik, K. Saluja","doi":"10.1109/ATS.2005.101","DOIUrl":"https://doi.org/10.1109/ATS.2005.101","url":null,"abstract":"Three issues that are dominating test research today are test application time, test data volume and test power. Researchers have focused on these issues mostly considering the popular serial scan architecture for its relatively low hardware overhead while ignoring the fact that exponential drop in hardware cost offers opportunities for implementing a test architecture that previously may have been unacceptable. This paper takes such a paradigm shift into account and studies the simultaneous solution of all three problems of serial scan by making use of progressive random access scan test architecture. This architecture only increases the hardware cost marginally while providing marked improvements for the three issues. This paper explains the test architecture and then develops a test generation methodology which reduces the test application time by nearly 75%, test data volume by 50% for the benchmark circuits. Above all, the architecture is inherently so efficient that it reduces the test power by nearly 99% or more of the test power consumption compared to serial scan","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114517413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
CryptoScan: A Secured Scan Chain Architecture CryptoScan:一个安全的扫描链架构
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.42
Debdeep Mukhopadhyay, Shibaji Banerjee, D. R. Chowdhury, B. Bhattacharya
{"title":"CryptoScan: A Secured Scan Chain Architecture","authors":"Debdeep Mukhopadhyay, Shibaji Banerjee, D. R. Chowdhury, B. Bhattacharya","doi":"10.1109/ATS.2005.42","DOIUrl":"https://doi.org/10.1109/ATS.2005.42","url":null,"abstract":"Scan based testing is a powerful and popular test technique. However the scan chain can be used by an attacker to decipher the cryptogram. The present paper shows such a side-channel attack on LFSR-based stream ciphers using scan chains. The paper subsequently discusses a strategy to build the scan chains in a tree based pattern with a selfchecking compactor. It has been shown that such a structure prevents such scan based attacks but does not compromise on fault coverage.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116036125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Random Jitter Testing Using Low Tap-Count Delay Lines 随机抖动测试使用低抽头计数延迟线
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.93
Jiun-Lang Huang
{"title":"Random Jitter Testing Using Low Tap-Count Delay Lines","authors":"Jiun-Lang Huang","doi":"10.1109/ATS.2005.93","DOIUrl":"https://doi.org/10.1109/ATS.2005.93","url":null,"abstract":"In this paper, a low-cost and process-insensitive random jitter testing algorithm is proposed for on-chip design-for-test applications. The algorithm incurs low hardware cost as it utilizes a low tap-count delay line to extract the RMS jitter information. Furthermore, the proposed algorithm can tolerate reasonable delay line deviations. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line deviations","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116579884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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