A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture

Abstract

To reduce the test application time and the test data volume in full-scan testing, various methods are proposed which utilize some additional built-in circuits dedicated for testing. In contrast, a previous method, called Reduced Scan Shift, does not utilize any additional built-in hardware. However, the method relies on scan chain flip-flop reordering, which is not always applicable. In this paper, we propose a test data sequence generation method for Reduced Scan Shift without scan chain flip-flop reordering. Our method fully utilizes justification technique and don't-care bits in test vectors.