Random Jitter Testing Using Low Tap-Count Delay Lines

Abstract

In this paper, a low-cost and process-insensitive random jitter testing algorithm is proposed for on-chip design-for-test applications. The algorithm incurs low hardware cost as it utilizes a low tap-count delay line to extract the RMS jitter information. Furthermore, the proposed algorithm can tolerate reasonable delay line deviations. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line deviations