{"title":"Improving Logic Test Quality of Microprocessors","authors":"S. Chakravarty","doi":"10.1109/ATS.2005.69","DOIUrl":"https://doi.org/10.1109/ATS.2005.69","url":null,"abstract":"Intel's aggressive process technology, used in manufacturing high-end microprocessors, is adding to the already difficult task of meeting very low DPM targets at an acceptable cost. This talk focuses on the challenges in improving productivity and meeting DPM goals for the logic part of our design, as opposed to the cache and I/O sections. We examine the entire HVM test flow and discuss on-going work to improve logic test quality and also highlight research problems that needs solution to achieve our goal","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"116 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120918429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage","authors":"V. Devanathan","doi":"10.1109/ATS.2005.82","DOIUrl":"https://doi.org/10.1109/ATS.2005.82","url":null,"abstract":"In very deep submicron era, high transition fault coverage is crucial to ensure low levels of Defective Parts Per Million(DPPM). In this paper, the role of bi-partitioning a netlist for transition fault test is analyzed and novel bi-partitioned scan architectures are proposed to improve transition fault coverage with slow speed scan enable. Experiments on 5 industrial ASIC designs show a consistent increase in transition fault coverage.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127791586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High Level Test Generation for Custom Hardware: An Industrial Perspective","authors":"Indradeep Ghosh","doi":"10.1109/ATS.2005.65","DOIUrl":"https://doi.org/10.1109/ATS.2005.65","url":null,"abstract":"This talk focuses on an industrial effort to generate sequential test patterns automatically from functional register transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level. The RTL circuit is assumed to be described in some high level description language (HDL) like VHDL or Verilog which is currently a standard practice in industrial ASIC designs. Currently only block level circuits of the order of tens of thousands of HDL lines are targeted","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130437086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, C. Su, Jwu-E Chen
{"title":"Finite State Machine Synthesis for At-Speed Oscillation Testability","authors":"Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, C. Su, Jwu-E Chen","doi":"10.1109/ATS.2005.60","DOIUrl":"https://doi.org/10.1109/ATS.2005.60","url":null,"abstract":"In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing, which makes delay-inducing defects detectable. (2) The ATPG is much easier, and the test set is usually smaller. (3) There is no need to store output responses, which greatly reduces the communication bandwidth between the Automatic Test Equipment (ATE) and Circuit under Test (CUT). We provide a register design that supports the oscillation test, and give an effective algorithm for oscillation test generation. Experimental results on MCNC benchmarks show that the proposed test method achieves high fault coverage with smaller number of test vectors.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127372254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wang Yong-sheng, W. Jin-xiang, Lai Feng-chang, Ye Yi-zheng
{"title":"Optimal Schemes for ADC BIST Based on Histogram","authors":"Wang Yong-sheng, W. Jin-xiang, Lai Feng-chang, Ye Yi-zheng","doi":"10.1109/ATS.2005.86","DOIUrl":"https://doi.org/10.1109/ATS.2005.86","url":null,"abstract":"Two testing time reducing schemes of histogram-based BIST (built-in self test) for testing of ADC IPs (intellectual property) are presented in this paper. The first technique uses parallel time decomposition to minimize not only chip area overhead but also testing time in the ADC BIST based on histogram. The second scheme named fold linear histogram-based BIST is proposed to further reduce testing time during computation of DNL (differential nonlinearity) and INL (integral nonlinearity) with little hardware overhead increase. Pseudo-algorithms are given to derive DNL, INL, offset and gain error. A practical implementation is described and the performance is evaluated","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126804996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Arithmetic Test Strategy for FFT Processor","authors":"Ji-Xue Xiao, Guang-Ju Chen, Yong-Le Xie","doi":"10.1109/ATS.2005.25","DOIUrl":"https://doi.org/10.1109/ATS.2005.25","url":null,"abstract":"For Fast Fourier Transform (FFT) processors, this paper presents a novel pseudo-exhaustive test strategy, in which adders in FFT processor generate all the test patterns. The scheme can detect all combinational faults within every basic building cell of FFT processors. Because of the reuse of some building blocks such as adders and registers existing in FFT processor, and the regularity of the circuit structure, the test scheme can be implemented at-speed and in parallel without performance degradation and additional hardware overhead, and with minimal additional area overhead..","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115205979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Family of Logical Fault Models for Reversible Circuits","authors":"I. Polian, Thomas Fiehn, B. Becker, J. Hayes","doi":"10.1109/ATS.2005.9","DOIUrl":"https://doi.org/10.1109/ATS.2005.9","url":null,"abstract":"Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not wellsuited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k- CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133104693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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