Improving Logic Test Quality of Microprocessors

Abstract

Intel's aggressive process technology, used in manufacturing high-end microprocessors, is adding to the already difficult task of meeting very low DPM targets at an acceptable cost. This talk focuses on the challenges in improving productivity and meeting DPM goals for the logic part of our design, as opposed to the cache and I/O sections. We examine the entire HVM test flow and discuss on-going work to improve logic test quality and also highlight research problems that needs solution to achieve our goal