{"title":"一种新的双分区扫描体系结构,提高迁移故障覆盖率","authors":"V. Devanathan","doi":"10.1109/ATS.2005.82","DOIUrl":null,"url":null,"abstract":"In very deep submicron era, high transition fault coverage is crucial to ensure low levels of Defective Parts Per Million(DPPM). In this paper, the role of bi-partitioning a netlist for transition fault test is analyzed and novel bi-partitioned scan architectures are proposed to improve transition fault coverage with slow speed scan enable. Experiments on 5 industrial ASIC designs show a consistent increase in transition fault coverage.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage\",\"authors\":\"V. Devanathan\",\"doi\":\"10.1109/ATS.2005.82\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In very deep submicron era, high transition fault coverage is crucial to ensure low levels of Defective Parts Per Million(DPPM). In this paper, the role of bi-partitioning a netlist for transition fault test is analyzed and novel bi-partitioned scan architectures are proposed to improve transition fault coverage with slow speed scan enable. Experiments on 5 industrial ASIC designs show a consistent increase in transition fault coverage.\",\"PeriodicalId\":373563,\"journal\":{\"name\":\"14th Asian Test Symposium (ATS'05)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"14th Asian Test Symposium (ATS'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2005.82\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"14th Asian Test Symposium (ATS'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2005.82","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage
In very deep submicron era, high transition fault coverage is crucial to ensure low levels of Defective Parts Per Million(DPPM). In this paper, the role of bi-partitioning a netlist for transition fault test is analyzed and novel bi-partitioned scan architectures are proposed to improve transition fault coverage with slow speed scan enable. Experiments on 5 industrial ASIC designs show a consistent increase in transition fault coverage.