High Level Test Generation for Custom Hardware: An Industrial Perspective

Abstract

This talk focuses on an industrial effort to generate sequential test patterns automatically from functional register transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level. The RTL circuit is assumed to be described in some high level description language (HDL) like VHDL or Verilog which is currently a standard practice in industrial ASIC designs. Currently only block level circuits of the order of tens of thousands of HDL lines are targeted