{"title":"超低DPM缺陷导向测试","authors":"V. Iyengar, P. Nigh","doi":"10.1109/ATS.2005.44","DOIUrl":null,"url":null,"abstract":"Business demand for ultra-low defects-permillion (DPM) levels and the emergence of subtle defects that often manifest as functional errors only in the presence of certain specific environmental conditions such as crosstalk, have led to a critical need for intelligent, adaptive, and targeted defectoriented test. The classical model of test, in which integrated circuits (ICs) are subjected to a blanket suite of stuck-fault, transition and Iddq test patterns generated without consideration to layout and chip-to-chip differences are now insufficient to bring DPM levels for cutting-edge ICs down to the requisite 10-100 range demanded by qualityconscious customers.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Defect-Oriented Test for Ultra-Low DPM\",\"authors\":\"V. Iyengar, P. Nigh\",\"doi\":\"10.1109/ATS.2005.44\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Business demand for ultra-low defects-permillion (DPM) levels and the emergence of subtle defects that often manifest as functional errors only in the presence of certain specific environmental conditions such as crosstalk, have led to a critical need for intelligent, adaptive, and targeted defectoriented test. The classical model of test, in which integrated circuits (ICs) are subjected to a blanket suite of stuck-fault, transition and Iddq test patterns generated without consideration to layout and chip-to-chip differences are now insufficient to bring DPM levels for cutting-edge ICs down to the requisite 10-100 range demanded by qualityconscious customers.\",\"PeriodicalId\":373563,\"journal\":{\"name\":\"14th Asian Test Symposium (ATS'05)\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"14th Asian Test Symposium (ATS'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2005.44\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"14th Asian Test Symposium (ATS'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2005.44","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Business demand for ultra-low defects-permillion (DPM) levels and the emergence of subtle defects that often manifest as functional errors only in the presence of certain specific environmental conditions such as crosstalk, have led to a critical need for intelligent, adaptive, and targeted defectoriented test. The classical model of test, in which integrated circuits (ICs) are subjected to a blanket suite of stuck-fault, transition and Iddq test patterns generated without consideration to layout and chip-to-chip differences are now insufficient to bring DPM levels for cutting-edge ICs down to the requisite 10-100 range demanded by qualityconscious customers.