Practical Aspects of Delay Testing for Nanometer Chips

Abstract

As SoC feature sizes are moving down to the nanometer range there is an increasing need to develop high quality, cost-effective and sensitive tests for nanometer devices. Many of the newer defects like resistive vias and bridges exhibit defective timing behavior, and require the usage of the transition fault model and sophisticated control of the launch-to-capture timings to the equivalent of system speeds.