14th Asian Test Symposium (ATS'05)最新文献_第5页

A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations 参数变化下管道电路面积约束成品率提高的统计方法

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.16

A. Datta, S. Bhunia, S. Mukhopadhyay, K. Roy

引用次数: 6

Flash Memory Die Sort by a Sample Classification Method 基于样本分类方法的闪存芯片排序

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.61

Yu-Chun Dawn, J. Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen

{"title":"Flash Memory Die Sort by a Sample Classification Method","authors":"Yu-Chun Dawn, J. Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen","doi":"10.1109/ATS.2005.61","DOIUrl":"https://doi.org/10.1109/ATS.2005.61","url":null,"abstract":"As the memory cells keep scaling down and designs are getting bigger and faster, uncertainty is becoming one of the greatest challenges for the semiconductor industry. Unexpected and unpredictable behaviors of devices usually lead to poor quality and reliability. Low-cost test techniques that improves die sorting accuracy thus are critical for advanced devices. Flash memory is more prone to such problem compared with others. Large capacity, high density, and complicated cell structure makes flash memory cell behavior difficult to predict precisely. Even when we test the dies on the same wafer it can be bothering, as each of them may ask for different test condition due to geometric process variation. As a fast and easy-to-use method to solve the problem, we propose a sample classification method. It is not only effective for flash memory testing, but also for other types of circuits that face similar test problem. Experimental result shows that the method solves the flash memory die sort problem efficiently and accurately. The test time is greatly reduced-for an industrial chip, the test time is reduced from 8,817 ms to 718 ms. Moreover, the proposed approach is also suitable for design-for-testability (DFT) implementation that can easily be integrated with a commodity or embedded memory.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"2 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126097042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST 利用加权扫描使能信号提高基于扫描的BIST的有效性

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.112

D. Xiang, Mingjing Chen, H. Fujiwara

引用次数: 1

Concurrent Test Generation 并发测试生成

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.39

V. Agrawal, Alok S. Doshi

引用次数: 9

Embedded Test Technology - Brief History, Current Status, and Future Directions 嵌入式测试技术——简史、现状和未来方向

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.56

J. Rajski

{"title":"Embedded Test Technology - Brief History, Current Status, and Future Directions","authors":"J. Rajski","doi":"10.1109/ATS.2005.56","DOIUrl":"https://doi.org/10.1109/ATS.2005.56","url":null,"abstract":"The conference theme of ITC 2005 focuses on evolutionary as well as revolutionary trends in test technology. It states: \"Recent advances in areas such as on-chip compression, low-cost test, and data analysis have burst onto the scene and are being rapidly and widely adopted\". Indeed, test compression is one of the fastest adopted DFT methodologies. It had been researched for ten years before it was commercially introduced four years ago, and now it has become the mainstream DFT technology. Just a couple of years ago, before on-chip test compression was introduced, it was broadly believed that Logic BIST was going to be the next generation DFT methodology for manufacturing test. There were three main advantages of test compression over Logic BIST that contributed to its rapid adoption: simplicity of the design flow that does not require test points or x-bounding logic, excellent manageable and predictable test quality, and significant reduction of cost of test. Compression of volume of test data and test time by several orders of magnitude combined with on-chip PLLs controlling at-speed capture allow for dramatic reduction of cost of test. Disruptive technology of this magnitude has impact that goes far beyond cost of manufacturing test. Test compression has changed competitive landscape, opened up completely new opportunities in product quality and yield management, and has redefined DFT technology roadmaps. It stimulates research and development activities in new areas that until now were considered not promising or not practical, enables quality of testing that was unachievable until now, accelerates adoption of new fault models that take into account physical data bases and timing information, and changes how fault diagnostics and yield learning are done in manufacturing environment. The presentation will discuss many of these issues, new opportunities, new and not so new challenges, as well as future technology roadmaps.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128995776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On Improving Defect Coverage of Stuck-at Fault Tests 提高卡在故障测试的缺陷覆盖率

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.84

K. Miyase, Kenta Terashima, S. Kajihara, X. Wen, S. Reddy

{"title":"On Improving Defect Coverage of Stuck-at Fault Tests","authors":"K. Miyase, Kenta Terashima, S. Kajihara, X. Wen, S. Reddy","doi":"10.1109/ATS.2005.84","DOIUrl":"https://doi.org/10.1109/ATS.2005.84","url":null,"abstract":"Recently design for manufacturability (DFM) has been required to achieve higher process yield. Information obtained from silicon by testing and/or fault analysis is sometimes fed back for redesign of VLSI circuits. In this paper we propose a method to maximize defect coverage of a test set initially generated for stuck-at faults in a full scan sequential circuit by using feed back information from fault analysis. If a test set for more complex faults than stuck-at faults is generated, higher defect coverage would be obtained. Such a test set, however, would have a large number of test vectors, and hence the test costs would go up. The proposed method improves defect coverage of the test set by not adding new test vectors but modifying test vectors with the information obtained from fault analysis. Therefore there are no negative impacts on test data volume and test application time. The initial fault coverage for stuck-at faults of the test set is guaranteed with modified test vectors. In this paper we focus on detecting as many as possible non-feedback AND/OR-type bridging faults. Experimental results show that the proposed method significantly decreases the number of non-feedback AND/OR-type bridging faults undetected by a test set generated for stuck-at faults","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121257102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Low-cost Production Test of BER for Wireless Receivers 无线接收机误码率的低成本生产测试

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.78

Achintya Halder, A. Chatterjee

引用次数: 10

Compressing Functional Tests for Microprocessors 微处理器的压缩功能测试

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.38

K. J. Balakrishnan, N. Touba, S. Patil

引用次数: 11

DFT for Low Cost SOC Test DFT用于低成本SOC测试

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.51

R. Parekhji

引用次数: 1

Challenges in Next Generation Mixed-Signal IC Production Testing 下一代混合信号集成电路生产测试的挑战

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.34

S. Cherubal

引用次数: 4