并发测试生成

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI:10.1109/ATS.2005.39

V. Agrawal, Alok S. Doshi

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引用次数: 9

摘要

我们为组合电路定义了一种新的测试类型，称为“并发测试”。给定一组目标故障，并发测试是检测集合中所有(或大多数)故障的输入向量。当为从独立故障折叠中获得的故障集生成并发测试时，可以预期最少或接近最少的测试。本文提出了基于仿真的独立故障崩溃和单故障ATPG并发测试的新方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Concurrent Test Generation

We define a new type of test, called "concurrent test," for a combinational circuit. Given a set of target faults, a concurrent-test is an input vector that detects all (or most) faults in the set. When concurrent tests are generated for fault sets obtained from independence fault collapsing, minimal or near-minimal tests can be expected. This paper gives new simulation-based methods for independence fault collapsing and for deriving concurrent tests using single-fault ATPG.

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14th Asian Test Symposium (ATS'05)

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