Embedded Test Technology - Brief History, Current Status, and Future Directions

J. Rajski
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Abstract

The conference theme of ITC 2005 focuses on evolutionary as well as revolutionary trends in test technology. It states: "Recent advances in areas such as on-chip compression, low-cost test, and data analysis have burst onto the scene and are being rapidly and widely adopted". Indeed, test compression is one of the fastest adopted DFT methodologies. It had been researched for ten years before it was commercially introduced four years ago, and now it has become the mainstream DFT technology. Just a couple of years ago, before on-chip test compression was introduced, it was broadly believed that Logic BIST was going to be the next generation DFT methodology for manufacturing test. There were three main advantages of test compression over Logic BIST that contributed to its rapid adoption: simplicity of the design flow that does not require test points or x-bounding logic, excellent manageable and predictable test quality, and significant reduction of cost of test. Compression of volume of test data and test time by several orders of magnitude combined with on-chip PLLs controlling at-speed capture allow for dramatic reduction of cost of test. Disruptive technology of this magnitude has impact that goes far beyond cost of manufacturing test. Test compression has changed competitive landscape, opened up completely new opportunities in product quality and yield management, and has redefined DFT technology roadmaps. It stimulates research and development activities in new areas that until now were considered not promising or not practical, enables quality of testing that was unachievable until now, accelerates adoption of new fault models that take into account physical data bases and timing information, and changes how fault diagnostics and yield learning are done in manufacturing environment. The presentation will discuss many of these issues, new opportunities, new and not so new challenges, as well as future technology roadmaps.
嵌入式测试技术——简史、现状和未来方向
ITC 2005的会议主题侧重于测试技术的进化和革命趋势。报告称:“芯片上压缩、低成本测试和数据分析等领域的最新进展已经出现,并正在迅速被广泛采用。”实际上,测试压缩是最快被采用的DFT方法之一。经过十年的研究,直到四年前才被商业化,现在已经成为主流的DFT技术。就在几年前,在片上测试压缩被引入之前,人们普遍认为Logic BIST将成为制造测试的下一代DFT方法。与逻辑BIST相比,测试压缩有三个主要优点,这有助于它的快速采用:设计流程的简单性,不需要测试点或x边界逻辑,出色的可管理和可预测的测试质量,以及显著降低测试成本。将测试数据量和测试时间压缩几个数量级,并结合片上锁相环控制高速捕获,从而大大降低了测试成本。这种规模的颠覆性技术的影响远远超出了制造测试的成本。测试压缩改变了竞争格局,在产品质量和产量管理方面开辟了全新的机会,并重新定义了DFT技术路线图。它刺激了到目前为止被认为没有希望或不实用的新领域的研究和开发活动,实现了迄今为止无法实现的测试质量,加速了考虑物理数据库和定时信息的新故障模型的采用,并改变了在制造环境中进行故障诊断和产量学习的方式。该演讲将讨论许多这些问题,新的机遇,新的和不太新的挑战,以及未来的技术路线图。
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