14th Asian Test Symposium (ATS'05)最新文献_第4页

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor 使用周期性可变的MUXs减压器减少扫描数据量

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.96

Yinhe Han, Xiaowei Li, S. Swaminathan, Yu Hu, A. Chandra

引用次数: 12

Challenges in High Speed Interface Testing 高速接口测试中的挑战

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.33

S. Abdennadher, S. Shaikh

引用次数: 2

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle 基于路径延迟惯性原理的互连线路串扰故障检测

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.41

M. Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu

引用次数: 0

On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models 数字电路的n-检测和桥接故障模型在线测试

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.85

S. Biswas, P. Srikanth, R. Jha, S. Mukhopadhyay, A. Patra, D. Sarkar

引用次数: 20

Enhancing Fault Simulation Performance by Dynamic Fault Clustering 动态故障聚类提高故障仿真性能

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.58

S. Mirkhani, Z. Navabi

{"title":"Enhancing Fault Simulation Performance by Dynamic Fault Clustering","authors":"S. Mirkhani, Z. Navabi","doi":"10.1109/ATS.2005.58","DOIUrl":"https://doi.org/10.1109/ATS.2005.58","url":null,"abstract":"Fault simulation algorithms used for large designs propagate a list of faults instead of a single fault in each simulation. Concurrent (Ulrich and Baker, 1974) and deductive (Armstrong, 1972) fault simulation algorithms are two examples of this kind of algorithm. In this paper, we utilize an optimization concept, which can be added to fault list propagating algorithms. In this concept, faults can be grouped into several disjoint fault sets. All faults in a group affect every line of the circuit in a similar way. Fault clustering is performed dynamically, based on a particular test vector, during the fault simulation process. This method causes less memory fragmentation, since there are a limited number of fault groups in each simulation time. On the other hand, it reduces faulty circuit calculation in fault simulation process compared with the traditional fault simulation methods. In addition, the generality of this concept makes it useful for behavioral fault simulation methods as well as traditional gate-level ones. We have implemented this method in the VHDL environment and tested it on ISCAS'85 benchmarks. Experimental results show that in large circuits the performance is at least doubled by this technique","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132287637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops 通过重新配置扫描触发器来设计具有成本效益的扫描测试

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.46

D. Xiang, Kaiwei Li, H. Fujiwara

引用次数: 7

An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications 计算密集型应用的高效系统级到RTL验证框架

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.24

N. Liveris, H. Zhou, P. Banerjee

引用次数: 2

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency 基于部分强可测试性的RTL数据路径DFT方法以保证完全故障效率

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.8

Hiroyuki Iwata, T. Yoneda, S. Ohtake, H. Fujiwara

引用次数: 7

New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors 新的自检输出重复展位乘法器，具有高故障覆盖率的软错误

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.80

D. Marienfeld, E. Sogomonyan, V. Ocheretnij, M. Gössel

引用次数: 13

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing ISC:低功耗测试的可重构扫描单元架构

14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.72

H. Esmaeilzadeh, S. Shamshiri, P. Saeedi, Z. Navabi

{"title":"ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing","authors":"H. Esmaeilzadeh, S. Shamshiri, P. Saeedi, Z. Navabi","doi":"10.1109/ATS.2005.72","DOIUrl":"https://doi.org/10.1109/ATS.2005.72","url":null,"abstract":"Violation of power constraints in the test mode may cause permanent failure in a circuit. Thus, Low power testing is essential for low power circuits. This paper proposes a reconfigurable scan-cell architecture that eliminates the propagation of unnecessary transitions during shift-in and shift-out. The proposed reconfigurable scanpath rearranges its latches to mask its outputs when a test-vector/test-result shifts in/out to/from. The rearrangement is performed without any need to extra latches or buffers. In fact, the native latches of a basic scan-path are reconfigured to keep the outputs of the scan-path (inputs of the combinational cloud) intact in the shifting phase. A few primitive gates are required for the rearrangement of the latches which means that the architecture has a low area overhead. The rearrangement implies that even and odd bits of test-vectors/test-results are interleaved in the shifting, and then, we called this reconfigurable architecture Interleaved Scan-Cell (ISC). The proposed scan-cell supports all required operations such as scan-in, scan-out, test-vector application, and test-result collection. The reconfigurable interleaved scan-path is inserted in a number of ISCAS benchmark circuits and the total area overhead and test power consumptions are presented. The results and comparisons show that using interleaved scancell architecture reduces test power dissipation while it has a low area overhead. Also, it is shown that the proposed scan-cell architecture adds a negligible delay to the propagation time of the scan-path registers and thus does not alter the clock frequency.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125736527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0