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Bridge Defect Diagnosis with Physical Information 基于物理信息的桥梁缺陷诊断
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.32
Wei Zou, Wu-Tung Cheng, S. Reddy
{"title":"Bridge Defect Diagnosis with Physical Information","authors":"Wei Zou, Wu-Tung Cheng, S. Reddy","doi":"10.1109/ATS.2005.32","DOIUrl":"https://doi.org/10.1109/ATS.2005.32","url":null,"abstract":"Circuit behavior in the presence of bridge defects is affected by three factors: bridge resistance, drive strength of bridged signals and the threshold voltages of downstream gates. Current bridge defect diagnosis methods either ignore all of these factors or consider drive strengths and/or threshold voltages only. Specifically, existing diagnosis methods have not considered the effect caused by bridge resistance. So the diagnosis results from current procedures may not be as accurate as possible. In this paper, we present a bridge defect diagnosis method taking all three factors into account. Experiments conducted on benchmark circuits and one industrial design demonstrate that the proposed method can achieve a very high diagnosis accuracy and resolution.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121181536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability 基于连续可测性的soc功耗约束面积和时间协同优化
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.88
T. Yoneda, Hisakazu Takakuwa, H. Fujiwara
{"title":"Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability","authors":"T. Yoneda, Hisakazu Takakuwa, H. Fujiwara","doi":"10.1109/ATS.2005.88","DOIUrl":"https://doi.org/10.1109/ATS.2005.88","url":null,"abstract":"This paper presents a design-for-testability method that transforms a given SoC into consecutively testable one under power constraint. When a power constraint and a user defined importance ratio between area overhead and test time are given, the proposed method can create an optimal TAM design and a test schedule for the importance ratio under the power constraint with low computational cost. Experimental results show that the proposed method can achieve area and time co-optimization under power constraint. Moreover, the proposed method can obtain better results for SoCs without power constraint compared to test bus method and our previous method based on consecutive testability of SoCs","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123877384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Robust Built-In Test of RF ICs Using Envelope Detectors 使用包络检测器的射频集成电路鲁棒内置测试
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.95
Donghoon Han, A. Chatterjee
{"title":"Robust Built-In Test of RF ICs Using Envelope Detectors","authors":"Donghoon Han, A. Chatterjee","doi":"10.1109/ATS.2005.95","DOIUrl":"https://doi.org/10.1109/ATS.2005.95","url":null,"abstract":"To address growing production test costs, a low-cost built-in test solution for RF circuits is proposed that is robust to process, supply voltage and temperature variations (PVT variations). The test solution consists of measuring the envelope of the output response to a two-tone test stimulus. This is a relatively low frequency signal compared to the nominal frequency of the RF device under test (DUT) and can therefore be sampled using an on-chip ADC. The resulting test response waveform is analyzed using wavelet transforms. The corresponding wavelet coefficients are used to accurately predict the test specification values of the RF DUT in the presence of noise. The proposed test approach has been demonstrated for a 2.4GHz low noise amplifier designed in a 0.18mum CMOS process and shows high prediction accuracy for the test specifications of the DUT in the presence of noise and PVT variations","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117256727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
A 5 Gbps Wafer-Level Tester 5 Gbps晶圆级测试仪
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.5
A. Majid, D. Keezer, J. V. Karia
{"title":"A 5 Gbps Wafer-Level Tester","authors":"A. Majid, D. Keezer, J. V. Karia","doi":"10.1109/ATS.2005.5","DOIUrl":"https://doi.org/10.1109/ATS.2005.5","url":null,"abstract":"This paper describes an economical approach to highspeed testing of high-density wafer-level packaged logic devices. The solution assumes that the devices to be tested have built-in self-test features, thereby reducing the complexity of functional testing required. This also reduces the need for expensive automated test equipment (ATE). A stand alone miniature tester is developed and connected to the top of a wafer probe card with multiple high-speed (2-5 Gbps) signals. To keep costs low, the tester uses off-theshelf components. However its performance in some aspects exceeds that of traditional ATE. Measurements illustrate the tester generating programmable 5Gbps signals with a +25ps timing accuracy. The generated signals exhibit low jitter 50ps and have a rise time of about 120ps.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122973195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test 一种用于极压应力测试的CMOS运算放大器的设计
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.49
Shaolei Quan, Qiang Qiang, C. Wey
{"title":"Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test","authors":"Shaolei Quan, Qiang Qiang, C. Wey","doi":"10.1109/ATS.2005.49","DOIUrl":"https://doi.org/10.1109/ATS.2005.49","url":null,"abstract":"Previous work on extreme-voltage stress test of analog ICs has suffered either from time-costly circuit-level simulation or from the considerable number of bits in the control signal added to circuit for stress operation. This paper presents several fully-stressable circuit structures the appropriate use of which in analog ICs eliminates the need for extra control bits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18µm CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with minor performance degradation.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122851869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Automatic Generation of Basis Set of Path for Path Testing 路径测试中路径基集的自动生成
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.106
Guangmei Zhang, Chen Rui, Xiaowei Li, Congying Han
{"title":"The Automatic Generation of Basis Set of Path for Path Testing","authors":"Guangmei Zhang, Chen Rui, Xiaowei Li, Congying Han","doi":"10.1109/ATS.2005.106","DOIUrl":"https://doi.org/10.1109/ATS.2005.106","url":null,"abstract":"Basis set of path is consisted of some of the program’s paths. The automatic generation method of basis set of path is discussed in this paper. It is built by searching the control flow graph of a program by depth-first searching method. In order to avoiding that the algorithm will never stop and reducing the searching procedure, the sub-path from the multi-indegree nodes to the end node of a program and the sub-path that contains a loop is recorded during the construction of a basis path. Some new basis paths can be constructed by merging these two kinds of sub-paths.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129743570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
DFT Aware Layout - Layout Aware DFT DFT感知布局-布局感知DFT
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.50
S. Taneja
{"title":"DFT Aware Layout - Layout Aware DFT","authors":"S. Taneja","doi":"10.1109/ATS.2005.50","DOIUrl":"https://doi.org/10.1109/ATS.2005.50","url":null,"abstract":"The era of the SOC and sub 100nm process technologies has created several new sets of challenges for the test engineer. One of these is the return to prominence of the effect of test infrastructure on the overall physical design of the device. This time it is not impact of logic overhead which is at the top of the list but the need for DFT to interact with the design implementation process at multiple critical points. Whether it is the floorplanning of MBIST controllers, the placement of MISR structures for test signature capture, the extraction of detailed timing for delay testing, the identification of candidates for bridge fault testing, even the use of testing diagnostics in the development of an effective DFM/DFY strategy, the interactions between test engineering and layout engineering are demanding new levels of integration. This talk will identify some of these areas, discuss ways in which they can be addressed, and a few of the consequences if they aren’t.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"63 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116438178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes 使用超过100个节点的计算网格验证工业设计
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.113
S. Iyer, J. Jain, D. Sahoo, Takeshi Shimizu
{"title":"Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes","authors":"S. Iyer, J. Jain, D. Sahoo, Takeshi Shimizu","doi":"10.1109/ATS.2005.113","DOIUrl":"https://doi.org/10.1109/ATS.2005.113","url":null,"abstract":"Formal verification, especially error detection, is rapidly increasing in importance with the rising complexity of designs. The main constraint in verification is the total amount of resources available - both time as well as memory. Most attempts at verification only use a single processor. Recently, various attempts have been made to use parallel and distributed methods for verification. However, verification in a Grid-based environment has not yet been very widely adopted. As personal computers gain in computing capacity, the concept of computation grids is gaining acceptance. Here, a grid is a network of machines that may not be dedicated to a specific computational use, but may only be available some of the time. This is a unique environment where massive parallelism is possible by using otherwise idle CPU cycles from a large number of computers. Such processors may even be in geographically diverse locations. We describe a Grid-based verifi- cation environment for detecting errors in a design. We verify user-written assertions as well as properties, e.g. unreachable code, index-out-of-range, that are extracted automatically from the design using a state-of-the-art HDL parser. Such an approach can help the user to quickly find RTL level bugs earlier in the design cycle.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126891171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Managing Test and Repair of Embedded Memory Subsystem in SoC SoC中嵌入式存储子系统的测试与维修管理
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.79
R. Chandramouli
{"title":"Managing Test and Repair of Embedded Memory Subsystem in SoC","authors":"R. Chandramouli","doi":"10.1109/ATS.2005.79","DOIUrl":"https://doi.org/10.1109/ATS.2005.79","url":null,"abstract":"This presentation discusses one such IIP targeted towards the test and repair of embedded memories. An advanced technique called the STARtrade (self test and repair) memory system embedded on-chip diagnoses failed memory bits and repairs the failed memory in real time using the redundant resources (row or columns or both) in the memory. The STAR processor itself has four key test and repair functions. They are BIST (built-in-self-test) to create memory specific test patterns, a BIST diagnostics to analyze and identify the failure, BIRA (built-in redundancy analysis), and the repair and redundancy allocation logic with algorithms to reconfigure the memory rows and columns to be topologically efficient post repair","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Flip-flop chaining architecture for power-efficient scan during test application 触发器链结构，在测试应用期间进行节能扫描
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.62
S. Gupta, Tarang Vaish, S. Chattopadhyay
{"title":"Flip-flop chaining architecture for power-efficient scan during test application","authors":"S. Gupta, Tarang Vaish, S. Chattopadhyay","doi":"10.1109/ATS.2005.62","DOIUrl":"https://doi.org/10.1109/ATS.2005.62","url":null,"abstract":"Power dissipation in CMOS circuits during test time poses a crucial bottleneck for circuit performance and robustness. The power consumption due to switching activity while scan-in of test vectors and scan-out of responses is of particular concern. In this paper a methodology for scan chain modification and test vector adaptation is proposed to effectively reduce the scan test power consumption by controlling this switching activity. Proposed approach, unlike the many in published literature, does not incorporate reordering of scan cells; thus avoiding timing and routing overheads. ATPG software ATALANTA was used for test vector generation. The algorithm was verified for ISCAS’89 benchmark circuits, where it showed as much as 27.3% of reduction in switching activity during scan operations.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"os-41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127870307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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