{"title":"一种用于极压应力测试的CMOS运算放大器的设计","authors":"Shaolei Quan, Qiang Qiang, C. Wey","doi":"10.1109/ATS.2005.49","DOIUrl":null,"url":null,"abstract":"Previous work on extreme-voltage stress test of analog ICs has suffered either from time-costly circuit-level simulation or from the considerable number of bits in the control signal added to circuit for stress operation. This paper presents several fully-stressable circuit structures the appropriate use of which in analog ICs eliminates the need for extra control bits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18µm CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with minor performance degradation.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test\",\"authors\":\"Shaolei Quan, Qiang Qiang, C. Wey\",\"doi\":\"10.1109/ATS.2005.49\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Previous work on extreme-voltage stress test of analog ICs has suffered either from time-costly circuit-level simulation or from the considerable number of bits in the control signal added to circuit for stress operation. This paper presents several fully-stressable circuit structures the appropriate use of which in analog ICs eliminates the need for extra control bits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18µm CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with minor performance degradation.\",\"PeriodicalId\":373563,\"journal\":{\"name\":\"14th Asian Test Symposium (ATS'05)\",\"volume\":\"219 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"14th Asian Test Symposium (ATS'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2005.49\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"14th Asian Test Symposium (ATS'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2005.49","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test
Previous work on extreme-voltage stress test of analog ICs has suffered either from time-costly circuit-level simulation or from the considerable number of bits in the control signal added to circuit for stress operation. This paper presents several fully-stressable circuit structures the appropriate use of which in analog ICs eliminates the need for extra control bits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18µm CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with minor performance degradation.
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