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Threshold testing: Covering bridging and other realistic faults 阈值测试:涵盖桥接和其他实际故障
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.108
Zhigang Jiang, S. Gupta
{"title":"Threshold testing: Covering bridging and other realistic faults","authors":"Zhigang Jiang, S. Gupta","doi":"10.1109/ATS.2005.108","DOIUrl":"https://doi.org/10.1109/ATS.2005.108","url":null,"abstract":"In the recent years, yields for digital VLSI chips have been declining and the decline is expected to accelerate. We have recently proposed a new testing approach called threshold testing, with the goal of providing acceptable yields in future processes for a wide range of high performance digital applications, including audio, speech, video, graphics, visualization, games, and wireless communication. The motivation of this paper is to answer the following question: Do threshold tests generated for stuck-at faults provide as high a threshold coverage for realistic faults as the classical coverage for realistic faults provided by classical stuck-at test sets? Using a combination of analysis and experiments, we show that the stuck-at fault model is indeed a suitable model for threshold testing. This opens the way for developing low cost tools for threshold testing that will provide high threshold coverage for realistic faults, and hence help provide higher yields in future processes at low costs. We also present a threshold automatic test pattern generator (ATPG) for bridging faults.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123532948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Cost Optimal Design of Nonlinear CA based PRPG for Test Applications 基于非线性CA的PRPG测试成本优化设计
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.40
Sukanta Das, H. Rahaman, B. Sikdar
{"title":"Cost Optimal Design of Nonlinear CA based PRPG for Test Applications","authors":"Sukanta Das, H. Rahaman, B. Sikdar","doi":"10.1109/ATS.2005.40","DOIUrl":"https://doi.org/10.1109/ATS.2005.40","url":null,"abstract":"This paper reports a scheme for cost optimal design of PRPG, built around nonlinear cellular automata (CM). The characterization of 3-neighborhood CA rules provides the foundation of designing the n-bit PRPG in linear time. The GA (genetic algorithm) framework proposed to evolve the CA results in a minimal cost PRPG structure, in terms of area overhead and delay","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121891027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Untestable Multi-Cycle Path Delay Faults in Industrial Designs 工业设计中不可测试的多周期路径延迟故障
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.111
M. Syal, M. Hsiao, S. Natarajan, S. Chakravarty
{"title":"Untestable Multi-Cycle Path Delay Faults in Industrial Designs","authors":"M. Syal, M. Hsiao, S. Natarajan, S. Chakravarty","doi":"10.1109/ATS.2005.111","DOIUrl":"https://doi.org/10.1109/ATS.2005.111","url":null,"abstract":"The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across latches results in signals which propagate across multiple clock cycles along paths with multiple latches. These paths need to be tested for delay failures to ensure reliability of performance. However, many of these multi-cycle paths can be untestable and significant computational effort is wasted in targeting such paths during test generation and fault grading. To save this computational effort, a-priori identification of untestable multicycle paths is desired. We address this issue in our paper through a novel and unique framework: unlike traditional techniques, which focus only on single-cycle path delay faults (for flip-flop based designs with single clock), our framework efficiently identifies untestable multi-cycle path delay faults (Mpdfs) in latch-based designs with multiple clocks. We use a novel graphical representation and sequential implications to identify non-robustly untestable M-pdfs through a three-step methodology. Results for industrial designs demonstrate the effectiveness and scalability of our framework.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122004017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Limitation of structural scan delay test 结构扫描延迟测试的局限性
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.74
T. M. Mak
{"title":"Limitation of structural scan delay test","authors":"T. M. Mak","doi":"10.1109/ATS.2005.74","DOIUrl":"https://doi.org/10.1109/ATS.2005.74","url":null,"abstract":"Beyond the traditional stuck-at fault model, there are transition fault model and path delay model, followed by many, many other fault models that have appeared over the years. Transition model essentially define a node that is slow to rise or slow to fall and that this slow transition make its way to a primary output. Meanwhile path delay fault is more precise and define that a slow event be propagated along specific paths to a particular primary output. Due to their name (transition/delay) and nature, these fault models would appear to detect structural delay faults (whether it is process induced or delay defect induced). There is a general belief in the industry that achieving good coverage with these models would guarantee high product quality.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117216136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Shortening Burn-In Test: Application of a Novel Approach in optimizing Burn-In Time using Weibull Statistical Analysis with HVST 缩短老化试验:利用威布尔统计分析优化老化时间的新方法与HVST的应用
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.99
M. F. Zakaria, Zainal Abu Kassim, M. Ooi, S. Demidenko
{"title":"Shortening Burn-In Test: Application of a Novel Approach in optimizing Burn-In Time using Weibull Statistical Analysis with HVST","authors":"M. F. Zakaria, Zainal Abu Kassim, M. Ooi, S. Demidenko","doi":"10.1109/ATS.2005.99","DOIUrl":"https://doi.org/10.1109/ATS.2005.99","url":null,"abstract":"Burn-in and stress testing are becoming increasingly important, a sine qua non in the electronics industry as customers become increasingly sensitive to failures occurring in the useful life of a product or system. Burn-in subjects the product to expected field extremes by exposing the product to accelerated temperature and voltages stress to screen infant mortalities (latent failures). In the past, burn in duration studies use constant failure rate statistics to model the classical bathtub curve describing early-life failure behavior of the product throughout its operating lifetime. Thus, FIT (Failure in Time) rate calculations were greatly inflated by including failures occurring long after the time of interest. This manifests in a requirement for a very low failure rate after the conservative burn-in stresses causes the need to sample larger number of units in order to differentiate between the passing and failing criteria. Furthermore, it makes the Burn-In study more complicated and reduces the chance of success.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124622701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Test Compaction for Pseudo-Random Testing 伪随机测试的有效测试压缩
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.55
Shenmin Zhang, S. Seth, B. Bhattacharya
{"title":"Efficient Test Compaction for Pseudo-Random Testing","authors":"Shenmin Zhang, S. Seth, B. Bhattacharya","doi":"10.1109/ATS.2005.55","DOIUrl":"https://doi.org/10.1109/ATS.2005.55","url":null,"abstract":"Compact set of 3-valued test vectors for random pattern resistant faults are covered in multiple test passes. During a pass, its associated test cube specifies certain bits in the scan chain to be held fixed and others to change pseudo -randomly. We propose an algorithm to find a small number of cubes to cover all the test vectors, thus minimizing total test length. The test-cube finding algorithm repeatedly evaluates small perturbations of the current solution so as to maximize the expected test coverage of the cube. Experimental results show that our algorithm covers the test vectors by test cubes that are one to two orders of magnitude smaller in number with a much smaller increase in the percentage of specified bits. It outperforms comparable schemes reported in the literature","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128228998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Block-based Schema-driven Assertion Generation for Functional Verification 用于功能验证的基于块的模式驱动断言生成
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.30
A. Hekmatpour, Azadeh Salehi
{"title":"Block-based Schema-driven Assertion Generation for Functional Verification","authors":"A. Hekmatpour, Azadeh Salehi","doi":"10.1109/ATS.2005.30","DOIUrl":"https://doi.org/10.1109/ATS.2005.30","url":null,"abstract":"Current assertion-based verification frameworks provide utilities to define assertions which are exercised during simulation. The traditional verification bottleneck of test generation, simulation, debug, and coverage analysis has been shifted but not eliminated. Defining assertions, ensuring their completeness and accuracy and maintaining a large number of assertions has proven to be the new verification bottleneck. We present a system for automatic assertion generation based on the blocklevel structural analysis of the design description. For each class of design HDL constructs, a verification assertion schema is instantiated into the design description. The system can also analyze existing assertions and identify missing or inconsistent ones. Users can select assertion schemas from the library or define new schema for a project. The resulting assertions are optimized for the target verification environment. A prototype of the system called SocVer has been developed for System-on-a-Chip interface and interconnect assertion generation and optimization.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131338722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Boundary Value Testing based on UML Models 基于UML模型的边界值测试
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.31
P. Samuel, R. Mall
{"title":"Boundary Value Testing based on UML Models","authors":"P. Samuel, R. Mall","doi":"10.1109/ATS.2005.31","DOIUrl":"https://doi.org/10.1109/ATS.2005.31","url":null,"abstract":"We present a novel method to automatically generate test cases based on UML state chart specifications. In our approach, we transform the conditional predicates on state transitions and apply function minimization technique to generate the test data. We use boundary value testing methods to generate effective test cases that satisfy test coverage criteria like full predicate coverage criteria and transition path coverage criteria. Our approach achieves adequate test coverage without unduly increasing the number of test cases. The test cases are generated for class as well as cluster level testing.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126892724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
An Effective Design for Hierarchical Test Generation Based on Strong Testability 基于强可测试性的分层测试生成的有效设计
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.23
H. Ichihara, T. Inoue, Naoki Okamoto, Toshinori Hosokawa, H. Fujiwara
{"title":"An Effective Design for Hierarchical Test Generation Based on Strong Testability","authors":"H. Ichihara, T. Inoue, Naoki Okamoto, Toshinori Hosokawa, H. Fujiwara","doi":"10.1109/ATS.2005.23","DOIUrl":"https://doi.org/10.1109/ATS.2005.23","url":null,"abstract":"Hierarchical test generation is an efficient method of test generation for VLSI circuits. In this paper, we study a test plan generation algorithm for hierarchical test based on strong testability. We propose a heuristic algorithm for finding a control forest requiring a small number of hold functions by improving an existing test plan generation algorithm based on strong testability. Experimental results show that the proposed algorithm is effective in reducing additional hold functions, i.e., reducing hardware overhead and delay penalty of datapaths","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"669 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123382628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression 基于片上时钟和测试压缩的纳米soc低成本延迟测试
14th Asian Test Symposium (ATS'05) Pub Date : 2005-12-18 DOI: 10.1109/ATS.2005.75
Hiroyuki Nakamura, Akio Shirokane, Y. Nishizaki, A. Uzzaman, V. Chickermane, B. Keller, Tsutomu Ube, Yoshihiko Terauchi
{"title":"Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression","authors":"Hiroyuki Nakamura, Akio Shirokane, Y. Nishizaki, A. Uzzaman, V. Chickermane, B. Keller, Tsutomu Ube, Yoshihiko Terauchi","doi":"10.1109/ATS.2005.75","DOIUrl":"https://doi.org/10.1109/ATS.2005.75","url":null,"abstract":"Testing at-speed delay defects is difficult on a speed constrained low cost tester. This paper describes the use of a clock chopper based onproduct clocking circuitry and interfaces to delay ATPG to achieve reliable test patterns. We also describe the test compression methods used to address the problem of increased test data volume due to delay tests. Data is presented on several industrial circuits to demonstrate the effectiveness of these DFT methods on nanometer designs. Our results show that a seamless combination of atspeed delay testing with compression can help to test the nanometer defects at a very competitive cost.","PeriodicalId":373563,"journal":{"name":"14th Asian Test Symposium (ATS'05)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126230554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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