A 5 Gbps Wafer-Level Tester

Abstract

This paper describes an economical approach to highspeed testing of high-density wafer-level packaged logic devices. The solution assumes that the devices to be tested have built-in self-test features, thereby reducing the complexity of functional testing required. This also reduces the need for expensive automated test equipment (ATE). A stand alone miniature tester is developed and connected to the top of a wafer probe card with multiple high-speed (2-5 Gbps) signals. To keep costs low, the tester uses off-theshelf components. However its performance in some aspects exceeds that of traditional ATE. Measurements illustrate the tester generating programmable 5Gbps signals with a +25ps timing accuracy. The generated signals exhibit low jitter 50ps and have a rise time of about 120ps.