ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing

Abstract

Violation of power constraints in the test mode may cause permanent failure in a circuit. Thus, Low power testing is essential for low power circuits. This paper proposes a reconfigurable scan-cell architecture that eliminates the propagation of unnecessary transitions during shift-in and shift-out. The proposed reconfigurable scanpath rearranges its latches to mask its outputs when a test-vector/test-result shifts in/out to/from. The rearrangement is performed without any need to extra latches or buffers. In fact, the native latches of a basic scan-path are reconfigured to keep the outputs of the scan-path (inputs of the combinational cloud) intact in the shifting phase. A few primitive gates are required for the rearrangement of the latches which means that the architecture has a low area overhead. The rearrangement implies that even and odd bits of test-vectors/test-results are interleaved in the shifting, and then, we called this reconfigurable architecture Interleaved Scan-Cell (ISC). The proposed scan-cell supports all required operations such as scan-in, scan-out, test-vector application, and test-result collection. The reconfigurable interleaved scan-path is inserted in a number of ISCAS benchmark circuits and the total area overhead and test power consumptions are presented. The results and comparisons show that using interleaved scancell architecture reduces test power dissipation while it has a low area overhead. Also, it is shown that the proposed scan-cell architecture adds a negligible delay to the propagation time of the scan-path registers and thus does not alter the clock frequency.