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Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献

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High-density reachability analysis 高密度可达性分析
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480006
Kavita Ravi, F. Somenzi
{"title":"High-density reachability analysis","authors":"Kavita Ravi, F. Somenzi","doi":"10.1109/ICCAD.1995.480006","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480006","url":null,"abstract":"We address the problem of reachability analysis for large finite state systems. Symbolic techniques have revolutionized reachability analysis but still have limitations in traversing large systems. We present techniques to improve the symbolic breadth-first traversal and compute a lower bound on the reachable states. We identify the problem as one of density during traversal and our techniques seek to improve the same. Our results show a marked improvement on the existing breadth-first traversal methods.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128245409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 165
New algorithms for min-cut replication in partitioned circuits 分区电路中最小切割复制的新算法
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480015
Hannah Honghua Yang, D. F. Wong
{"title":"New algorithms for min-cut replication in partitioned circuits","authors":"Hannah Honghua Yang, D. F. Wong","doi":"10.1109/ICCAD.1995.480015","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480015","url":null,"abstract":"Hwang and El Gamal (1992, 1995) formulated the min-cut replication problem, which is to determine min-cut replication sets for the components of a k-way partition such that the cut size of the partition is minimized after the replication. They gave an optimal algorithm for finding min-cut replication sets for a k-way partitioned digraph. However, their optimal min-cut replication algorithm does not guarantee min-cut replication sets of minimum sizes. Furthermore, their algorithm is not optimal for hypergraphs. In this paper, we optimally solve the min-area min-cut replication problem on digraphs, which is to find min-cut replication sets with the minimum sizes. More importantly, we give an optimal solution to the hypergraph min-area min-cut replication problem using a much smaller flow network model. We implemented our algorithms in a package called Hyper-MAMC, and interfaced Hyper-MAMC to the TAPIR package. On average, Hyper-MAMC produces 57.3% fewer cut nets and runs much faster than MO-Rep in the TAPIR package, on the same initial partitions of a set of MCNC Partition93 benchmark circuits.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128179108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Hierarchical timing analysis using conditional delays 使用条件延迟的分层时序分析
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480143
H. Yalcin, John P. Hayes
{"title":"Hierarchical timing analysis using conditional delays","authors":"H. Yalcin, John P. Hayes","doi":"10.1109/ICCAD.1995.480143","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480143","url":null,"abstract":"We present a novel method to perform timing analysis of hierarchical circuits. It is based on the representation of circuit modules by conditional delay matrices (CDMs) which combine module delays with event propagation conditions. The CDM model is independent of module complexity and allows automatic identification of false paths. We exploit hierarchy information to perform efficient delay computation. The effectiveness of the method is demonstrated on a high-level model of the ISCAS-85 circuit c6288, which is difficult to analyze using traditional approaches. The method has been implemented in a symbolic timing analysis program called CAT. The application of CAT to carry-skip adders shows that hierarchical timing analysis is faster by an order of magnitude than gate-level analysis.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131684154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient use of large don't cares in high-level and logic synthesis 在高层和逻辑综合中有效地使用大的不在乎
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480023
R. Bergamaschi, D. Brand, L. Stok, Michel Berkelaar, S. Prakash
{"title":"Efficient use of large don't cares in high-level and logic synthesis","authors":"R. Bergamaschi, D. Brand, L. Stok, Michel Berkelaar, S. Prakash","doi":"10.1109/ICCAD.1995.480023","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480023","url":null,"abstract":"This paper describes optimization techniques using don't-care conditions that span the domain of high-level and logic synthesis. The following three issues are discussed: (1) how to describe and extract don't-care conditions from high-level descriptions; (2) how to pass don't-care conditions from high-level to logic synthesis; and (3) how to optimize the logic using don't-care conditions. Efficient techniques are given for these three problems which allow the use of large don't-care sets. Results from several examples demonstrate that these techniques are very effective for both area and delay minimization.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130392509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Phantom redundancy: a high-level synthesis approach for manufacturability 幻影冗余:可制造性的高级综合方法
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480199
B. Iyer, R. Karri, I. Koren
{"title":"Phantom redundancy: a high-level synthesis approach for manufacturability","authors":"B. Iyer, R. Karri, I. Koren","doi":"10.1109/ICCAD.1995.480199","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480199","url":null,"abstract":"Phantom redundancy, an area-efficient technique for fabrication-time reconfigurability is presented. Phantom redundancy adds extra interconnect so as to render the resulting microarchitecture reconfigurable in the presence of any (single) functional unit failure. The proposed technique yields partially good chips in addition to perfect chips. A genetic algorithm is used to incorporate phantom redundancy constraints into microarchitecture synthesis. The algorithm minimizes tire performance degradation due to any faulty functional unit of the resulting microarchitecture. The effectiveness of the technique is illustrated on benchmark examples.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133091248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Memory bank and register allocation in software synthesis for ASIPs api软件合成中的内存库和寄存器分配
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480145
A. Sudarsanam, S. Malik
{"title":"Memory bank and register allocation in software synthesis for ASIPs","authors":"A. Sudarsanam, S. Malik","doi":"10.1109/ICCAD.1995.480145","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480145","url":null,"abstract":"An architectural feature commonly found in digital signal processors (DSPs) is multiple data-memory banks. This feature increases memory bandwidth by permitting multiple memory accesses to occur in parallel when the referenced variables belong to different memory banks and the registers involved are allocated according to a strict set of conditions, Unfortunately, current compiler technology is unable to take advantage of the potential increase in parallelism offered by such architectures, Consequently, most application software for DSP systems is hand-written-a very time-consuming task. We present an algorithm which attempts to maximize the benefit of this architectural feature. While previous approaches have decoupled the phases of register allocation and memory bank assignment, our algorithm performs these two phases simultaneously. Experimental results demonstrate that our algorithm substantially improves the code quality of many compiler-generated and even hand-written programs.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132038524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 94
Constrained multivariable optimization of transmission lines with general topologies 具有一般拓扑结构的输电线路约束多变量优化
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480003
Rohinish Gupta, L. Pileggi
{"title":"Constrained multivariable optimization of transmission lines with general topologies","authors":"Rohinish Gupta, L. Pileggi","doi":"10.1109/ICCAD.1995.480003","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480003","url":null,"abstract":"The design of system level interconnects to meet signal integrity objectives is a challenging problem. This paper formulates the transmission line synthesis problem as a constrained multi-dimensional optimization of the complete net, taking into account factors like loading conditions on the line loss in the line and rise-time of the input signal. Different design variables such as width or resistivity of the interconnect, resistive source or far-end termination, etc. can all be considered concurrently. The termination metric is based upon forcing the impulse response waveform to be symmetric using the first three exact moments of the distributed system. An efficient means to trade-off between signal rise-time and ringing is presented and no time-domain simulations are needed. Several examples are presented to demonstrate the efficacy of the proposed methodology.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133795494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design verification via simulation and automatic test pattern generation 设计验证通过仿真和自动测试模式生成
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480009
H. Al-Asaad, J. Hayes
{"title":"Design verification via simulation and automatic test pattern generation","authors":"H. Al-Asaad, J. Hayes","doi":"10.1109/ICCAD.1995.480009","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480009","url":null,"abstract":"We present a simulation-based method for combinational design verification that aims at complete coverage of specified design errors using conventional ATPG tools. The error models used in prior research are examined and reduced to four types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), and wrong input errors (WIEs). Conditions are derived for a gate to be completely testable for GSEs. These conditions lend to small rest sets for GSEs. Near-minimal test sets are also derived for GCEs. We analyze redundancy in design errors and relate this to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. Our experiments demonstrate that high coverage of the modeled design errors can be achieved with small test sets.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121777330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Board-level multi-terminal net routing for FPGA-based logic emulation 基于fpga逻辑仿真的板级多终端网络路由
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480138
Wai-Kei Mak, D. F. Wong
{"title":"Board-level multi-terminal net routing for FPGA-based logic emulation","authors":"Wai-Kei Mak, D. F. Wong","doi":"10.1109/ICCAD.1995.480138","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480138","url":null,"abstract":"We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as the Realizer System (Varghese et al., (1993)) and the Enterprise Emulation System (Maliniak (1992)) manufactured by Quickturn Systems. Optimal algorithms have been proposed for the case where all nets are two-terminal nets. In this paper, we show how multi-terminal nets can be handled by decomposition into two-terminal nets. We show that the multi-terminal net decomposition problem can be modelled as a bounded-degree hypergraph-to-graph transformation problem where hyper-edges are transformed to spanning trees. A network flow-based algorithm that solves both problems is proposed. It determines if there is a feasible decomposition and gives one whenever such a decomposition exists.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121093336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
The formal verification of a pipelined double-precision IEEE floating-point multiplier 一个流水线双精度IEEE浮点乘法器的形式化验证
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479878
M. Aagaard, C. Seger
{"title":"The formal verification of a pipelined double-precision IEEE floating-point multiplier","authors":"M. Aagaard, C. Seger","doi":"10.1109/ICCAD.1995.479878","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479878","url":null,"abstract":"Floating-point circuits are notoriously difficult to design and verify. For verification, simulation barely offers adequate coverage, conventional model-checking techniques are infeasible, and theorem-proving based verification is not sufficiently mature. In this paper we present the formal verification of a radix-eight, pipelined, IEEE double-precision floating-point multiplier. The verification was carried out using a mixture of model-checking and theorem-proving techniques in the Voss hardware verification system. By combining model-checking and theorem-proving we were able to build on the strengths of both areas and achieve significant results with a reasonable amount of effort.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114701574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
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