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Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献

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Fast discrete function evaluation using decision diagrams 快速离散函数评估使用决策图
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480147
P. McGeer, K. McMillan, A. Saldanha, A. Sangiovanni-Vincentelli, P. Scaglia
{"title":"Fast discrete function evaluation using decision diagrams","authors":"P. McGeer, K. McMillan, A. Saldanha, A. Sangiovanni-Vincentelli, P. Scaglia","doi":"10.1109/ICCAD.1995.480147","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480147","url":null,"abstract":"An approach for fast discrete function evaluation based on multi-valued decision diagrams (MDD) is proposed. The MDD for a logic function is translated into a table on, which function evaluation is performed by a sequence of address lookups. The value of a function for a given input assignment is obtained with at most one lookup per input. The main application is to cycle-based logic simulation of digital circuits, where the principal difference from other logic simulators is that only values of the output and latch ports are computed. Theoretically, decision-diagram based function evaluation offers orders-of-magnitude potential speedup over traditional logic simulation methods. In practice, memory bandwidth becomes the dominant consideration on large designs. We describe techniques to optimize usage of the memory hierarchy.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116890610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 119
PARAS: System-level concurrent partitioning and scheduling PARAS:系统级并发分区和调度
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480153
W. Wong, R. Jain
{"title":"PARAS: System-level concurrent partitioning and scheduling","authors":"W. Wong, R. Jain","doi":"10.1109/ICCAD.1995.480153","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480153","url":null,"abstract":"Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (called PARAS) which can exploit this interaction by solving the scheduling and partitioning problems concurrently are presented. PARAS maximizes the overall performance of the final design and considers different chip configurations and communication structures. Experiments, conducted with specifications ranging in size from few to hundreds of operations, demonstrate the success of this approach.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125191890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm fiduccia - matthews算法初始分割的一种梯度方法
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480017
Lung-Tien Liu, M. Kuo, Shih-Chen Huang, Chung-Kuan Cheng
{"title":"A gradient method on the initial partition of Fiduccia-Mattheyses algorithm","authors":"Lung-Tien Liu, M. Kuo, Shih-Chen Huang, Chung-Kuan Cheng","doi":"10.1109/ICCAD.1995.480017","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480017","url":null,"abstract":"In this paper, a Fiduccia-Mattheyses (FM) algorithm incorporating a novel initial partition generating method is proposed. The proposed algorithm applies to both bipartitioning and multi-way partitioning problems with or without replication. The initial partition generating method is based on a gradient descent algorithm. On partitioning without replication, our algorithm achieves an average of 17% improvement over the analytical method, PARABOLI, on bipartitioning, 10% better than Primal-Dual method on 4-way partitioning and 51% better than net-based method. On partitioning allowing replication, our algorithm achieves an average of 23% improvement over the directed Fiduccia-Mattheyses algorithm on Replication Graph (FMRG) method on bipartitioning.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126058429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Synthesis of multiplier-less FIR filters with minimum number of additions 具有最少加法数的无乘法器FIR滤波器的合成
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480201
M. Mehendale, S. Sherlekar, G. Venkatesh
{"title":"Synthesis of multiplier-less FIR filters with minimum number of additions","authors":"M. Mehendale, S. Sherlekar, G. Venkatesh","doi":"10.1109/ICCAD.1995.480201","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480201","url":null,"abstract":"In this paper we present optimizing transformations to minimize the number of additions+subtractions in both the direct form (/spl Sigma/ A/sub i/X/sub n-i/ based) and its transposed form (Multiple Constant Multiplication based) implementation of FIR filters. These transformations are based on the iterative elimination of 2-bit common subexpressions in the coefficients binary representations. We give detailed description of the algorithms and present results for eight low pass FIR filters with the number of coefficients ranging from 16 to 128. The results show upto 35% reduction in the number of additions+subtractions to implement /spl Sigma/ A/sub i/X/sub n-i/ based FIR filter structures and upto 38% reduction to implement MCM based structures.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123738490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 102
Rectangle-packing-based module placement 基于矩形包装的模块放置
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480159
H. Murata, K. Fujiyoshi, S. Nakatake, Y. Kajitani
{"title":"Rectangle-packing-based module placement","authors":"H. Murata, K. Fujiyoshi, S. Nakatake, Y. Kajitani","doi":"10.1109/ICCAD.1995.480159","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480159","url":null,"abstract":"The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular modules of arbitrary site, place them without overlapping on a layer in the smallest bounding rectangle. Since the variety of the packing is infinite (two-dimensionally continuous) many, the key issue for successful optimization is in the introduction of a P-admissible solution space, which is a finite set of solutions at least one of which is optimal. This paper proposes such a solution space where each packing is represented by a pair of module name sequences. Searching this space by simulated annealing, hundreds of modules could be successfully packed as demonstrated. Combining a conventional wiring method, the biggest MCNC benchmark ami49 is challenged.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125336017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 424
Statistical behavioral modeling and characterization of A/D converters A/D转换器的统计行为建模和特性
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480172
E. Peralías, A. Rueda, J. Huertas
{"title":"Statistical behavioral modeling and characterization of A/D converters","authors":"E. Peralías, A. Rueda, J. Huertas","doi":"10.1109/ICCAD.1995.480172","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480172","url":null,"abstract":"This paper presents a method to characterize Nyquist rate A/D converters based on the use of a first order statistical behavioral model. The proposed model is derived from a very basic statistical interpretation of the conversion operation which contemplates noise and statistical process variations effects on traditional converter parameters. Both DC and dynamic converter parameters can be easily measured. The applicability of the proposed method is illustrated with two different examples. The first serves to show the possibility of deriving the statistical behavioral model from real measured data, and to prove the correctness of the model by comparing results to those obtained with traditional deterministic models. The second example illustrates the incorporation of the model in the mixed-signal simulator ELDO. The obtained results show that despite the model's simplicity, it is very efficient for quick and complete simulation of data converters.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115511068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Generating sparse partial inductance matrices with guaranteed stability 生成具有保证稳定性的稀疏部分电感矩阵
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479989
B. Krauter, L. Pileggi
{"title":"Generating sparse partial inductance matrices with guaranteed stability","authors":"B. Krauter, L. Pileggi","doi":"10.1109/ICCAD.1995.479989","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479989","url":null,"abstract":"This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding the smallest matrix terms, the proposed approach maintains accuracy at middle and high frequencies and is guaranteed to be positive definite for any degree of sparsity (thereby producing stable circuit solutions). While the proposed technique is strictly based upon potential theory (i.e. the invariance of potential differences on the zero potential reference choice), the technique is, nevertheless, presented and discussed in both circuit and magnetic terms. The conventional and the proposed sparse formulation techniques are contrasted in terms of eigenvalues and circuit simulation results on practical examples.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116396400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 108
Addressing high frequency effects in VLSI interconnects with full wave model and CFH 利用全波模型和CFH解决VLSI互连中的高频效应
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479990
R. Achar, M. Nakhla, Qi-jun Zhang
{"title":"Addressing high frequency effects in VLSI interconnects with full wave model and CFH","authors":"R. Achar, M. Nakhla, Qi-jun Zhang","doi":"10.1109/ICCAD.1995.479990","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479990","url":null,"abstract":"In order to accurately characterize dispersive system of VLSI interconnects at higher frequencies, full wave analysis which takes into account all possible field components and satisfies all boundary conditions is required. However, conventional circuit simulation of interconnects with full wave models is extremely CPU expensive. This paper presents a new method to extend the moment matching technique, complex frequency hopping, to the case of interconnects modeled with full wave analysis. Formulation of circuit equations is modified to incorporate interconnect stencil from full wave analysis. A new algorithm for the moment generation for interconnect networks with full wave models has been developed. Full wave analysis has been carried out with the efficient 'spectral domain approach'. Results have shown that the proposed method is accurate while it yields a speed up of one to three orders of magnitude over conventional simulation techniques.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122581183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On testable multipliers for fixed-width data path architectures 关于固定宽度数据路径架构的可测试乘法器
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480169
N. Mukherjee, J. Rajski, J. Tyszer
{"title":"On testable multipliers for fixed-width data path architectures","authors":"N. Mukherjee, J. Rajski, J. Tyszer","doi":"10.1109/ICCAD.1995.480169","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480169","url":null,"abstract":"The usage of multipliers in the increasingly demanding fixed-width data path architectures poses serious testability problems. Their truncated outputs not only degrade the fault observability, but the output responses of multipliers are inadequate to completely test functional blocks that are driven by them. In this paper, we propose a new design for testability scheme to improve the overall testability of data paths. The methodology takes into account the truncated least significant bits of the product in the test mode to increase the variety of patterns at the output of a multiplier. The proposed techniques are part of the Arithmetic Built-in Self Test methodology and can be incorporated with a minimal performance degradation and area overhead.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122081084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A controller-based design-for-testability technique for controller-data path circuits 一种基于控制器的可测试性设计技术，用于控制器数据路径电路
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480168
S. Dey, V. Gangaram, M. Potkonjak
{"title":"A controller-based design-for-testability technique for controller-data path circuits","authors":"S. Dey, V. Gangaram, M. Potkonjak","doi":"10.1109/ICCAD.1995.480168","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480168","url":null,"abstract":"This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controller and the data path parts are individually 100% testable, the composite circuit may not be easily testable by gate-level sequential ATPG. Analysis shows that a primary problem in test pattern generation of combined controller-data path circuits is the correlation of control signals due to implications imposed by the controller specification. A design-for-testability technique is developed to re-design the controller such that the implications which may produce conflicts during test pattern generation are eliminated. The DFT technique involves adding extra control vectors to the controller. Experimental results show the ability of the controller DFT technique to produce highly testable controller-data path circuits, with nominal hardware overhead.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"402 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129226214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
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