PARAS: System-level concurrent partitioning and scheduling

Abstract

Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (called PARAS) which can exploit this interaction by solving the scheduling and partitioning problems concurrently are presented. PARAS maximizes the overall performance of the final design and considers different chip configurations and communication structures. Experiments, conducted with specifications ranging in size from few to hundreds of operations, demonstrate the success of this approach.