Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献_第2页

An optimal algorithm for area minimization of slicing floorplans 切片平面图面积最小化的最优算法

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480160

W. Shi

引用次数: 9

Extracting RTL models from transistor netlists 从晶体管网络列表中提取RTL模型

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479879

K. J. Singh, P. Subrahmanyam

引用次数: 22

Bounded-skew clock and Steiner routing under Elmore delay Elmore延迟下的有界偏差时钟和斯坦纳路由

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479993

J. Cong, A. Kahng, Cheng-Kok Koh, C. Tsao

引用次数: 57

Interface co-synthesis techniques for embedded systems 嵌入式系统接口协同合成技术

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480024

P. Chou, R. Ortega, G. Borriello

{"title":"Interface co-synthesis techniques for embedded systems","authors":"P. Chou, R. Ortega, G. Borriello","doi":"10.1109/ICCAD.1995.480024","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480024","url":null,"abstract":"A key aspect of the synthesis of embedded systems is the automatic integration of system components. This entails the derivation of both the hardware and software interfaces that will bind these elements together and permit them to communicate correctly and efficiently. Without the automatic synthesis of these interfaces, designers are not able to fully simulate and evaluate their systems. Frequently, they are discouraged from exploring the design space of different hardware/software partitions because practical concerns mandate minimizing changes late in the design cycle, thus leading to more costly implementations than necessary. This paper presents a set of techniques that form the basis of a comprehensive solution to the synthesis of hardware/software interfaces. Software drivers and glue logic are generated to connect processors to peripheral devices, hardware co-processors, or communication interfaces while meeting bandwidth and performance requirements. We use as examples a set of devices that communicate over an infrared local communications network (highlighting a video wrist-watch display) to explain our techniques and the need for design space exploration tools for embedded systems.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133876961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 97

A fast wavelet collocation method for high-speed VLSI circuit simulation 高速VLSI电路仿真的快速小波配置方法

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480001

D. Zhou, N. Chen, W. Cai

引用次数: 15

A unified approach to topology generation and area optimization of general floorplans 总体平面图的拓扑生成和面积优化的统一方法

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480208

P. Dasgupta, S. Sur-Kolay, B. Bhattacharya

引用次数: 6

An iterative improvement algorithm for low power data path synthesis 低功耗数据路径合成的迭代改进算法

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480190

A. Raghunathan, N. Jha

{"title":"An iterative improvement algorithm for low power data path synthesis","authors":"A. Raghunathan, N. Jha","doi":"10.1109/ICCAD.1995.480190","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480190","url":null,"abstract":"We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects of several behavioral synthesis tasks like module selection, clock selection, scheduling and resource sharing on supply voltage and switched capacitance need to be considered simultaneously to fully derive the benefits of design space exploration at the behavior level. We present an efficient algorithm for performing scheduling, clock selection, module selection, and resource allocation and assignment simultaneously with an aim of reducing the power consumption in the synthesized data path. The algorithm, which is based on an iterative improvement strategy, is capable of escaping local minima in its search for a low power solution. The algorithm considers diverse module libraries and complex scheduling constructs such as multicycling chaining, and structural pipelining. We describe supply voltage and clock pruning strategies that significantly improve the efficiency of our algorithm by cutting down on the computational effort involved in exploring candidate supply voltages and clock periods that are unlikely to lead to the best solution. Experimental results are reported to demonstrate the effectiveness of the algorithm. Our techniques can be combined with other known methods of behavioral power optimization like data path replication and transformations, to result in a complete data path synthesis system for low power applications.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126579567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 73

A timing-driven data path layout synthesis with integer programming 时序驱动的数据路径布局综合与整数规划

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480209

Jaewon Kim, S. Kang

引用次数: 8

Functional test generation for delay faults in combinational circuits 组合电路中延迟故障的功能测试生成

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480204

I. Pomeranz, S. Reddy

引用次数: 36

Synthesizing Petri nets from state-based models 基于状态的模型合成Petri网

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480008

J. Cortadella, M. Kishinevsky, L. Lavagno, A. Yakovlev

{"title":"Synthesizing Petri nets from state-based models","authors":"J. Cortadella, M. Kishinevsky, L. Lavagno, A. Yakovlev","doi":"10.1109/ICCAD.1995.480008","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480008","url":null,"abstract":"This paper presents a method to synthesize labeled Petri nets from state-based models. Although state-based models (such as finite state machines) are a powerful formalism to describe the behavior of sequential systems, they cannot explicitly express the notions of concurrency, causality and conflict Petri nets can naturally capture these notions. The proposed method in based on deriving an elementary transition system (ETS) from a specification model. Previous work has shown that for any ETS there exists a Petri net with minimum transition count (one transition for each label) with a reachability graph isomorphic to the original ETS. This paper presents the first known approach to obtain an ETS from a non-elementary TS and derive a place-irredundant Petri net. Furthermore, by imposing constraints on the synthesis method, different classes of Petri nets can be derived from the same reachability graph (pure, free choice, unique choice). This method has been implemented and efficiently applied in different frameworks: Petri net composition, synthesis of Petri nets from asynchronous circuits, and resynthesis of Petri nets.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124904975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 85