A timing-driven data path layout synthesis with integer programming

Abstract

We propose an efficient data path synthesis algorithm which generates bit-sliced layouts. Since data path circuits have special characteristics which are different from those of random logic circuits, the dedicated synthesis system is required for efficient layouts. Our main goal in the data path synthesis is to satisfy the timing constraints of circuits as well as to reduce layout areas. Timing-driven placement and over-the-cell routing techniques are developed to generate data path modules. Also, signal interfaces between bit-slices are carefully considered to further reduce layout areas. Our synthesis techniques take advantage of the common characteristics of datapath structures under timing constraints and applies mixed integer linear programming approach to solve the problem. The superior results from our data path synthesis system are demonstrated through comparison with the layout results with the simulated annealing technique.