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Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献

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Efficient and accurate transient simulation in charge-voltage plane 高效、准确的电荷-电压平面瞬态仿真
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480000
A. Devgan
{"title":"Efficient and accurate transient simulation in charge-voltage plane","authors":"A. Devgan","doi":"10.1109/ICCAD.1995.480000","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480000","url":null,"abstract":"Transient simulation has traditionally been performed in current-voltage plane (with current and voltage as variables)for verification of integrated circuits and systems. This paper introduces techniques for efficient and accurate transient simulation in charge-voltage plane (with charge and voltage as variables). For integrated circuits, both simulation cost and overhead to increase accuracy are drastically reduced by performing simulations in charge-voltage plane. Adaptively controlled explicit simulation in charge-voltage plane is used to demonstrate the feasibility of the approach. Solution of circuit equations in charge-voltage plane is 10-20 times more efficient than in current-voltage plane. Furthermore, simulation accuracy can be increased at an incremental cost. As a result, ACES in charge-voltage plane provides speedups of 300/spl times/-5000/spl times/ or more over traditional circuit simulators with little or no loss in circuit timing accuracy.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114879581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient construction of binary moment diagrams for verifying arithmetic circuits 用于验证算术电路的二值矩图的有效构造
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479995
K. Hamaguchi, Akihito Morita, S. Yajima
{"title":"Efficient construction of binary moment diagrams for verifying arithmetic circuits","authors":"K. Hamaguchi, Akihito Morita, S. Yajima","doi":"10.1109/ICCAD.1995.479995","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479995","url":null,"abstract":"BDD-based approaches cannot handle some arithmetic functions such as multiplication efficiently, while Binary Moment Diagrams proposed by Bryant and Chen (1994) provide compact representations for those functions. They reported a BMD-based polynomial-time algorithm for verifying multipliers. This approach requires high-level information such as specifications to subcomponents. This paper presents a new technique called backward construction which can construct BMDs directly from circuit descriptions without any high-level information. The experiments show that the computation time for verifying for n-bit multipliers is approximately n/sup 4/. We have successfully verified 64-bit multipliers of several type in 3-6 hours with 46 Mbyte of memory on SPARCstation 10/51. This result outperforms previous BDD-based approaches for verifying multipliers.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129172867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 73
Instruction selection using binate covering for code size optimization 指令选择使用二进制覆盖的代码大小优化
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480146
S. Liao, S. Devadas, K. Keutzer, S. Tjiang
{"title":"Instruction selection using binate covering for code size optimization","authors":"S. Liao, S. Devadas, K. Keutzer, S. Tjiang","doi":"10.1109/ICCAD.1995.480146","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480146","url":null,"abstract":"We address the problem of instruction selection in code generation for embedded DSP microprocessors. Such processors have highly irregular data-paths, and conventional code generation methods typically result in inefficient code. Instruction selection can be formulated as directed acyclic graph (DAG) covering. Conventional methods for instruction selection use heuristics that break up the DAG into a forest of trees and then cover them independently. This breakup can result in suboptimal solutions for the original DAG. Alternatively, the DAG covering problem can be formulated as a binate covering problem, and solved exactly or heuristically using branch-and-bound methods. We show that optimal instruction selection on a PAG in the case of accumulator-based architectures requires a partial scheduling of nodes in the DAG, and we augment the binate covering formulation to minimize spills and reloads. We show how the irregular data transfer costs of typical DSP data-paths can be modeled in the binate covering formulation.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123739909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 95
Technology mapping for field-programmable gate arrays using integer programming 使用整数规划的现场可编程门阵列的技术映射
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480139
Amit Chowdhary, J. Hayes
{"title":"Technology mapping for field-programmable gate arrays using integer programming","authors":"Amit Chowdhary, J. Hayes","doi":"10.1109/ICCAD.1995.480139","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480139","url":null,"abstract":"We show that the FPGA technology mapping problem can be efficiently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety of FPGA logic block architectures. We present a compact MILP formulation for logic blocks based on lookup tables (LUTs) or multiplexes. We also show that the MILP formulation can be easily modified to optimize area delay, or a combination of both. We demonstrate that moderately large benchmark circuits can be mapped in a reasonable time using the MILP approach directly. For larger circuits, we propose a technique of partitioning a circuit prior to mapping, which drastically reduces the computation time with little or no loss in optimality.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130052689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Power estimation techniques for integrated circuits 集成电路的功率估计技术
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480162
F. Najm
{"title":"Power estimation techniques for integrated circuits","authors":"F. Najm","doi":"10.1109/ICCAD.1995.480162","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480162","url":null,"abstract":"With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: (1) the use of simplified delay models, and (2) modeling long-term behavior of logic signals with probabilities. The array of available techniques differ in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the different assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130788619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
Linear decomposition algorithm for VLSI design applications 线性分解算法在VLSI设计中的应用
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480016
Jianmin Li, J. Lillis, Chung-Kuan Cheng
{"title":"Linear decomposition algorithm for VLSI design applications","authors":"Jianmin Li, J. Lillis, Chung-Kuan Cheng","doi":"10.1109/ICCAD.1995.480016","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480016","url":null,"abstract":"We propose a unified solution to both linear placement and partitioning. Our approach combines the well-known eigenvector optimization method with the recursive max-flow min-cut method. A linearized eigenvector method is proposed to improve the linear placement. A hypergraph maxflow algorithm is then adopted to efficiently find the max-flow min-cut. In our unified approach, the max-flow min-cut provides an optimal ordered partition subject to the given seeds and the eigenvector placement provides heuristic information for seed selection. Experimental results on MCNC benchmarks show that our approach is superior to other methods for both linear placement and partitioning problems. On average, our approach yields an improvement of 45.1% over eigenvector approach in terms of total wire length, and yields an improvement of 26.9% over PARABOLI[6] in terms of cut size.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130618465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Estimation and bounding of energy consumption in burst-mode control circuits 突发模式控制电路中能量消耗的估计和边界
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479881
P. Beerel, K. Yun, S. Nowick, Pei-Chuan Yeh
{"title":"Estimation and bounding of energy consumption in burst-mode control circuits","authors":"P. Beerel, K. Yun, S. Nowick, Pei-Chuan Yeh","doi":"10.1109/ICCAD.1995.479881","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479881","url":null,"abstract":"This paper describes two techniques to quantify energy consumption of burst-mode asynchronous (clock-less) control circuits. The circuit specifications considered are extended burst-mode specifications, and the implementations are multi-level logic implementations whose outputs are guaranteed to be free of any voltage glitches (hazards). Both techniques use stochastic analysis to combine a small number of simulations in order to quantify average energy per external signal transition. The first technique uses N-valued simulation to derive mathematically tight upper and lower bounds of energy consumption. Using this technique we bound the effect of hazards under all possible operating conditions and environments for a given circuit. Additionally, to drive synthesis tools for low-power we propose a second technique that uses fixed-delay simulation to derive a realistic estimate of energy consumption within our derived upper and lower bounds. We demonstrate the feasibility of both these techniques on a variety of burst-mode control circuits used in an industrial-quality chip. Our preliminary results indicate that less than 5% of the power of typical multi-level burst-mode circuits can be attributed to hazards.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133798805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Switching activity analysis using Boolean approximation method 用布尔逼近法分析开关活动
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479880
T. Uchino, F. Minami, T. Mitsuhashi, N. Goto
{"title":"Switching activity analysis using Boolean approximation method","authors":"T. Uchino, F. Minami, T. Mitsuhashi, N. Goto","doi":"10.1109/ICCAD.1995.479880","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479880","url":null,"abstract":"This paper presents a novel algorithm to estimate the signal probability and switching activity at all nodes in a combinational logic circuit under a zero-delay model without constructing global BDDs. By using Taylor expansion technique, the first-order signal correlation effects due to reconvergent fan-out nodes are taken into account. High accuracy is achieved by considering the dependency of the signal probability and switching activity on each primary input. High speed is also achieved by using the incremental approach for probability calculation. Our approach is able to handle large circuits, since it does not need to construct global BDDs for the probability calculation. The analysis of the time complexity and the experimental results show the running time of our approach to be about 100 times shorter than that of the most accurate approach previously proposed and that our approach has comparable accuracy. The error of the total power estimation is about 0.5% on average.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130479924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture 兼容的类编码在Roth-Karp分解为双输出LUT架构
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480141
Juinn-Dar Huang, Jing-Yang Jou, W. Shen
{"title":"Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture","authors":"Juinn-Dar Huang, Jing-Yang Jou, W. Shen","doi":"10.1109/ICCAD.1995.480141","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480141","url":null,"abstract":"Roth-Karp decomposition is one of the most popular techniques for LUT-based FPGA technology mapping because it can decompose a node into a set of nodes with fewer numbers of fanins. In this paper, we show how to formulate the compatible class encoding problem in Roth-Karp decomposition as a symbolic-output encoding problem in order to exploit the feature of the two-output LUT architecture. Based on this formulation, we also develop an encoding algorithm to minimize the number of LUT's required to implement the logic circuit. Experimental results show that our encoding algorithm can produce promising results in the logic synthesis environment for the two-output LUT architecture.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130710551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Single-layer fanout routing and routability analysis for ball grid arrays 球栅阵列的单层扇出布线及可达性分析
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480175
Man-Fai Yu, W. Dai
{"title":"Single-layer fanout routing and routability analysis for ball grid arrays","authors":"Man-Fai Yu, W. Dai","doi":"10.1109/ICCAD.1995.480175","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480175","url":null,"abstract":"Fanout routing for Ball Grid Array (BGA) packages becomes non-trivial when the I/O pin count increases. When the number of I/Os gets larger and larger, the number of I/Os we can put on a package may not be limited by the available area but sometimes by the ability to fan them out on the next level of interconnect-the PCB or MCM substrate. This paper presents an efficient algorithm (EVENFANOUT) which generates the optimal uniform distribution of wires. We have found the three cuts that is decisive on the routability of the package using EVENFANOUT. These decisive cuts form the base for design optimization of the package.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"17 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114131010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
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