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Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献

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Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques 基于行为综合技术的周期性硬实时系统的ASIC实现成本优化
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480154
M. Potkonjak, W. Wolf
{"title":"Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques","authors":"M. Potkonjak, W. Wolf","doi":"10.1109/ICCAD.1995.480154","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480154","url":null,"abstract":"Modern applications are often defined as sets of several computational tasks. This paper presents a synthesis algorithm for ASIC implementations which realize multiple computational tasks under hard real-time deadlines. The algorithm analyzes constraints imposed by task sharing as well as the traditional datapath synthesis criteria. In particular we demonstrated an efficient technique to combine rate-monotonic scheduling, a widely used hard real-time systems scheduling discipline, with estimations and scheduling and allocation algorithms. Matching the number of bits in tasks assigned to the same processor was the most important factor in obtaining good designs. We have demonstrated the effectiveness of our algorithms on several multiple-task examples.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122718816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization 加速流水线电路通过门尺寸和时钟倾斜优化的组合
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480158
H. Sathyamurthy, S. Sapatnekar, J. Fishburn
{"title":"Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization","authors":"H. Sathyamurthy, S. Sapatnekar, J. Fishburn","doi":"10.1109/ICCAD.1995.480158","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480158","url":null,"abstract":"An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121276732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A formal approach to nonlinear analog circuit verification 非线性模拟电路验证的形式化方法
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480002
L. Hedrich, E. Barke
{"title":"A formal approach to nonlinear analog circuit verification","authors":"L. Hedrich, E. Barke","doi":"10.1109/ICCAD.1995.480002","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480002","url":null,"abstract":"This paper presents an approach to nonlinear dynamic analog circuit verification. The input-output behavior of two systems is analyzed to check whether they are functionally similar. The algorithm compares the implicit nonlinear state space descriptions of the two systems on the same or on different levels of abstraction by sampling the state spaces and by building a nonlinear one-to-one mapping of the state spaces. Some examples demonstrate the feasibility of our approach.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127748818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
CAD challenges in multimedia computing 多媒体计算中的CAD挑战
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480163
P. Lippens, V. Nagasamy, W. Wolf
{"title":"CAD challenges in multimedia computing","authors":"P. Lippens, V. Nagasamy, W. Wolf","doi":"10.1109/ICCAD.1995.480163","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480163","url":null,"abstract":"This tutorial surveys the present and future of multimedia computing systems and outlines new challenges for CAD presented by these systems. Multimedia computing is a challenging domain for several reasons: it requires both high computation rates and memory bandwidth; it is a multirate computing problem; and requires low-cost implementations for high-volume markets. As a result, the design of multimedia computing systems introduces new challenges for CAD at all levels of abstraction, ranging from layout to system design. After surveying the nature of the multimedia computing problem, we examine two experiences in multimedia computer design from a CAD perspective: the design of VLSI systems-on-chips for multimedia: and the successive refinement of an application from software to a high-volume chip using advanced CAD synthesis tools.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134647212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Clock distribution design and verification for PowerPC microprocessors PowerPC微处理器的时钟分配设计与验证
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479991
S. Ganguly, S. Hojat
{"title":"Clock distribution design and verification for PowerPC microprocessors","authors":"S. Ganguly, S. Hojat","doi":"10.1109/ICCAD.1995.479991","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479991","url":null,"abstract":"With the increase of clock speeds, clock skew has become a significant part of the cycle time of high speed microprocessors. While many clock tree routing techniques promise zero or minimal skew, algorithm assumptions or design methodology constraints often prevent a single approach from being suitable for the entire clock design. In this paper we describe a collection of strategies for designing low skew clock distributions. These techniques are applied at various levels of design (synthesis, placement, routing etc.) to yield clock distribution networks of acceptable skew for the two different clock design styles used by PowerPC processors. We also describe a static timing based approach for analyzing the clock network to detect the various clock violations of interest. Finally we outline current deficiencies in our methodology.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133854995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On adaptive diagnostic test generation 关于自适应诊断测试的生成
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480010
Yiming Gong, S. Chakravarty
{"title":"On adaptive diagnostic test generation","authors":"Yiming Gong, S. Chakravarty","doi":"10.1109/ICCAD.1995.480010","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480010","url":null,"abstract":"Adaptive diagnosis, a paradigm for diagnosis, is defined. A system based on this paradigm, for I/sub DDQ/ measurement based diagnosis of bridging faults, is reported. Experimental evaluation of the system shows it to be substantially superior to existing systems, especially for larger circuits.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115262915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Relaxation-based harmonic balance technique for semiconductor device simulation 基于弛豫的半导体器件仿真谐波平衡技术
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480206
B. Troyanovsky, Zhiping Yu, L. So, R. Dutton
{"title":"Relaxation-based harmonic balance technique for semiconductor device simulation","authors":"B. Troyanovsky, Zhiping Yu, L. So, R. Dutton","doi":"10.1109/ICCAD.1995.480206","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480206","url":null,"abstract":"Harmonic and intermodulation distortion effects play an important role in numerous analog applications, particularly in such areas as wireless communication systems. In this paper, we present a two-dimensional harmonic balance semiconductor device simulator which accurately models these nonlinear effects at the physical (drift-diffusion) level. The simulator is based on Stanford University's PISCES code, and supports the full range of physical models and features present in the time-domain version of the program. A modified block Gauss-Seidel-Newton nonlinear relaxation scheme is developed to efficiently handle the extremely large size of two-dimensional harmonic balance semiconductor device simulation problems.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"508 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123062001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Symbolic hazard-free minimization and encoding of asynchronous finite state machines 异步有限状态机的符号无危险最小化与编码
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480191
Robert M. Fuhrer, Bill Lin, S. Nowick
{"title":"Symbolic hazard-free minimization and encoding of asynchronous finite state machines","authors":"Robert M. Fuhrer, Bill Lin, S. Nowick","doi":"10.1109/ICCAD.1995.480191","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480191","url":null,"abstract":"This paper presents an automated method for the synthesis of multiple-input-change (MIC) asynchronous state machines. Asynchronous state machine design is subtle since, unlike synchronous synthesis, logic must be implemented without hazards, and state codes must be chosen carefully to avoid critical races. We formulate and solve an optimal hazard-free and critical race-free encoding problem for a class of MIC asynchronous state machines called burst-mode. Analogous to a paradigm successfully used for the optimal encoding of synchronous machines, the problem is formulated as an input encoding problem. Implementations are targeted to sum-of-product realizations. We believe this is the first general method for the optimal encoding of hazard-free MIC asynchronous state machines under a generalized fundamental mode of operation. Results indicate that improved solutions are produced, ranging up to 17% improvement.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123391436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Power vs. delay in gate sizing: conflicting objectives? 门尺寸的功率与延迟:冲突的目标?
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480157
S. Sapatnekar, Weitong Chuang
{"title":"Power vs. delay in gate sizing: conflicting objectives?","authors":"S. Sapatnekar, Weitong Chuang","doi":"10.1109/ICCAD.1995.480157","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480157","url":null,"abstract":"The problem of sizing gates for power-delay tradeoffs is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. The dynamic power as well as the short-circuit power are modeled, using notions of delay and transition density, and the optimization problem is formulated using notions of convex programming. Previous approaches have not modeled the short circuit power, and our experimental results show that the incorporation of this leads to counter-intuitive results where the minimum power circuit is not necessarily the minimum-sized circuit.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122816673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Address generation for memories containing multiple arrays 为包含多个数组的内存生成地址
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480164
H. Schmit, D. E. Thomas
{"title":"Address generation for memories containing multiple arrays","authors":"H. Schmit, D. E. Thomas","doi":"10.1109/ICCAD.1995.480164","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480164","url":null,"abstract":"This paper presents techniques for generating addresses for memories containing multiple arrays. Because these techniques rely on the inversion or rearrangement of address bits, they are faster and require less hardware to compute than offset addition. Use of these techniques can decrease effective access time to arrays and reduce address generation hardware. The primary drawback is that extra memory space is occasionally required by these techniques, but this extra memory space is on average only 4% and no worse than 25.2% of the utilized memory space. This amount of wasted address space is less than the amount required by similar techniques.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128765117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
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