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2007 Asia and South Pacific Design Automation Conference最新文献

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A Run-Time Memory Protection Methodology 一种运行时内存保护方法
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358035
Udaya Seshua, N. Bussa, B. Vermeulen
{"title":"A Run-Time Memory Protection Methodology","authors":"Udaya Seshua, N. Bussa, B. Vermeulen","doi":"10.1109/ASPDAC.2007.358035","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358035","url":null,"abstract":"In this paper we present a novel methodology to help debug memory corruption errors during application debug. In this methodology an optimal balance between hardware and software instrumentation is chosen to check at run-time all memory accesses made by an application. To achieve this balance a set of benchmark applications is first analyzed to determine their memory access patterns. The analysis results are used to make our approach low-cost both from a software performance penalty and a hardware area point-of-view. Experimental results show that our innovative approach typically requires less than 2% of a CPU in silicon area for a less than 1% run-time performance overhead. Our method is both low-cost and applicable to high performance microprocessors as well as time-constrained embedded systems.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132944597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Thermal-Aware 3D IC Placement Via Transformation 热感知3D集成电路的转换安置
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358084
J. Cong, Guojie Luo, Jieqian Wei, Yan Zhang
{"title":"Thermal-Aware 3D IC Placement Via Transformation","authors":"J. Cong, Guojie Luo, Jieqian Wei, Yan Zhang","doi":"10.1109/ASPDAC.2007.358084","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358084","url":null,"abstract":"3D IC technologies can help to improve circuit performance and lower power consumption by reducing wirelength. Also, 3D IC technology can be used to realize heterogeneous system-on-chip design, by integrating different modules together with less interference with each other. In this paper, we propose a novel thermal-aware 3D cell placement approach, named T3Place, based on transforming a 2D placement with good wirelength to a 3D placement, with the objectives of half-perimeter wirelength, through-the-silicon (TS) via number and temperature. T3Place is composed of two steps, transformation from a 2D placement to a 3D placement and the refinement of the resulting 3D placement. We proposed and compared several different transformation techniques, including local stacking transformation (LST), folding-2, folding-4 and window-based stacking/folding transformation, and concluded that (i) LST can generate 3D placements with the least wirelength, (ii) the folding-based transformations result in 3D placements with the fewest TS vias, and (iii) the window-based stacking/folding transformations provide good TS via number and wirelength tradeoffs. For example, with four device layers, LST can reduce the wirelength by over 2times compared to the initial 2D placement, while window-based stacking/folding can provide over 10times variation in terms of the TS via number, thus adaptive to different manufacturing ability for TS via density. Moreover, we proposed a novel relaxed conflict-net (RCN) graph-based layer assignment method to further refine the 3D placements. Compared to LST results, thermal-aware RCN graph-based layer assignment algorithm (r = 10%) can further reduce the maximum on-chip temperature by 37%, with only 6% TS via number increase and 8% wirelength increase.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130551514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 155
Model-based Programming Environment of Embedded Software for MPSoC 基于模型的MPSoC嵌入式软件编程环境
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358007
S. Ha
{"title":"Model-based Programming Environment of Embedded Software for MPSoC","authors":"S. Ha","doi":"10.1109/ASPDAC.2007.358007","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358007","url":null,"abstract":"A noble model-based programming environment of embedded software for MPSoC is proposed. By defining a common intermediate code (CIC), it separates modeling of the software and implementation optimized for target architecture. It also allows us to use diverse models for initial specification. Another feature is to provide multi-phase debugging capabilities: at the modeling stage, at the code generation stage, and at the simulation stage. Preliminary experiments with a Divx player confirm the feasibility and validity of the proposed technique.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132397073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 2.8-V Multibit Complex Bandpass ΔΣAD Modulator in 0.18μm CMOS 基于0.18μm CMOS的2.8 v多位复杂带通ΔΣAD调制器
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357958
H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, M. Hotta
{"title":"A 2.8-V Multibit Complex Bandpass ΔΣAD Modulator in 0.18μm CMOS","authors":"H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, M. Hotta","doi":"10.1109/ASPDAC.2007.357958","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.357958","url":null,"abstract":"A second-order multibit switched-capacitor (SC) complex bandpass ΔΣ AD modulator has been designed, fabricated and tested for application to low-IF receivers in wireless communication systems. We have employed two new algorithms there to improve the signal-to-noise-and-distortion (SNDR) of the modulator, (i) A complex bandpass filter with I, Q dynamic matching to reduce the mismatch influence between I, Q paths. As its by-product, the complex modulator can be divided into two separate parts without signal line crossing between the upper and lower paths. Therefore, the layout design of the modulator can be greatly simplified; (ii) A new complex bandpass data-weighted averaging (DWA) algorithm is implemented to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy. Implemented in a 0.18-μm CMOS process and at 2.8V supply, the modulator achieves a measured peak SNDR of 64.5dB at 20MS/s with a signal bandwidth of 78kHz while dissipating 28.4mW and occupying an area of 1.82mm2.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124808414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology 基于90nm CMOS技术的10Gbps/通道片上信号电路与阻抗无与伦比的CML驱动
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357970
T. Kuboki, A. Tsuchiya, H. Onodera
{"title":"A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology","authors":"T. Kuboki, A. Tsuchiya, H. Onodera","doi":"10.1109/ASPDAC.2007.357970","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.357970","url":null,"abstract":"An on-chip signaling system consists of a CML driver, a differential transmission-line and a CML receiver is fabricated. We developed an impedance-unmatched driver for power reduction. The impedance-unmatched driver reduces the tail current of the CML buffer by tuning the load resistance. The designed circuit achieves 3mm, 10Gbps/channel on-chip signal transmission and the impedance-unmatched driver saves the energy per bit by 21% compared with a conventional impedance-matched driver.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130048010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Configurable AMBA On-Chip Real-Time Signal Tracer 可配置的AMBA片上实时信号跟踪器
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357967
Chung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang
{"title":"Configurable AMBA On-Chip Real-Time Signal Tracer","authors":"Chung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang","doi":"10.1109/ASPDAC.2007.357967","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.357967","url":null,"abstract":"This paper purpose an embedded AMBA signal tracer for microprocessor-based SoC's. This tracer provides five trace resolution modes that can perform a cycle-accurate or a transaction-based trace collection in an unlimited time. Also this tracer is implemented in a Soft-IP style. It provides four parameters for tracing configuration. The experimental results show that the bus tracer can reach a good compression ratio of 96%.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130274998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G) 基于移动多媒体引擎SoC (S1G)的低功耗ISDB-T单段解码器开发
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358059
K. Mori, M. Suzuki, Y. Ohara, S. Matsuo, A. Asano
{"title":"Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G)","authors":"K. Mori, M. Suzuki, Y. Ohara, S. Matsuo, A. Asano","doi":"10.1109/ASPDAC.2007.358059","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358059","url":null,"abstract":"TOSHIBA has developed mobile multi-media engine SoC, we call as S1G, which can realize low power ISDB-T one-segment decode in 42mW for eight months short period of time. Since MPEG2 TS (transport stream) de-multiplexing, AAC decoding and H.264 decoding should be simultaneously processed in ISDB-T one-segment decode, two TOSHIBA MeP (media embedded processor) processors and one DSP and hardware blocks are used effectively with pipeline operation in this LSI. Although it is generally considered that dedicated hardware accelerator should be used to realize low power operation for ISDB-T one-segment decode, TOSHBA succeeded in developing low power ISDB-T one-segment decoder using maximum software resources.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130323797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Multi-Drop Transmission-Line Interconnect in Si LSI
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357969
J. Seita, Hiroyuki Ito, K. Okada, Takashi Sato, K. Masu
{"title":"A Multi-Drop Transmission-Line Interconnect in Si LSI","authors":"J. Seita, Hiroyuki Ito, K. Okada, Takashi Sato, K. Masu","doi":"10.1109/ASPDAC.2007.357969","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.357969","url":null,"abstract":"This paper proposes a branching method for on-chip transmission line (TL) interconnects, which can reduce delay and power of global interconnects. A 6-mm-long TL interconnect with a branch is fabricated by using a 0.18 mum standard Si CMOS process, and the measurement result performs 4Gbps signal transmission.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130041880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability 可制造性/可靠性物理设计的最新研究和新挑战
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357992
Chung-Wei Lin, Ming-Chao Tsai, Kuang‐Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang
{"title":"Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability","authors":"Chung-Wei Lin, Ming-Chao Tsai, Kuang‐Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang","doi":"10.1109/ASPDAC.2007.357992","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.357992","url":null,"abstract":"As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical design for manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this paper, we introduce major challenges arising from nanometer process technology, survey key existing techniques for handling the challenges, and provide some future research directions in physical design for manufacturability and reliability.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129565902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Towards scalable and secure execution platform for embedded systems 面向嵌入式系统的可扩展、安全的执行平台
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358010
Hiroaki Inoue, M. Edahiro, J. Sakai
{"title":"Towards scalable and secure execution platform for embedded systems","authors":"Hiroaki Inoue, M. Edahiro, J. Sakai","doi":"10.1109/ASPDAC.2007.358010","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358010","url":null,"abstract":"Reliability of embedded systems can be enhanced by multicore and partitioning approaches. Physical partitioning based on AMP multicore achieves runtime stability of multiple applications in a system and prevents the whole system shutdown as well even when a malicious code creeps in. Combined with logical partitioning by processor visualization and SMP technologies, the multicore architecture could realize more flexible and more scalable platform for future embedded systems.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126346693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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