2007 Asia and South Pacific Design Automation Conference最新文献_第7页

Fault Dictionary Size Reduction for Million-Gate Large Circuits 百万栅极大型电路的故障字典缩减

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358092

Y. Hong, Juinn-Dar Huang

引用次数: 6

Deeper Bound in BMC by Combining Constant Propagation and Abstraction 结合常量传播和抽象的BMC深度界

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358003

R. Armoni, L. Fix, Ranan Fraer, T. Heyman, Moshe Y. Vardi, Y. Vizel, Yael Zbar

引用次数: 5

Exploration of Low Power Adders for a SIMD Data Path SIMD数据路径低功耗加法器的探索

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358106

Giacomo Paci, P. Marchal, L. Benini

引用次数: 2

Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains 下一代设计和EDA挑战:小物理、大系统和高工具链

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357772

Rob A. Rutenbar

{"title":"Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains","authors":"Rob A. Rutenbar","doi":"10.1109/ASPDAC.2007.357772","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.357772","url":null,"abstract":"There is much discussion of two challenges in the design of tomorrow’s electronics: the difficult “small physics” of nanoscale transistors, and the silicon/software complexity of “big systems”. But those of us who want to build beautiful algorithms have an additional hurdle: “tall tool-chains”. If it takes 50 tool-steps to build an industrial-strength design flow, and each tool is based on 1-2 “big algorithms”, does this mean that each new algorithm idea is worth, at best, 1-2% of the success of a design? This seems to me a bad way of accounting for the tremendous value that EDA brings to the world of design. How can we have a big impact in this important technology area? In this talk, I will offer several pieces of advice for how not to get buried by the tall-toolchain problem. I will discuss how to identify design problems that can have large impact, how to embrace the strange physics of tomorrow’s silicon technologies in the service of building beautiful algorithms, and how to get fresh (and unique) insights on problems by spending time working with a real design team. I will use design examples ranging from lithography, to computational finance, to silicon-based speech recognition, to illustrate the point that this is an exciting time to be working on tomorrow’s tool and design challenges.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"41 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114009334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Trace Compaction using SAT-based Reachability Analysis 使用基于sat的可达性分析的跟踪压缩

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358109

Sean Safarpour, A. Veneris, Hratch Mangassarian

引用次数: 16

Topology exploration for energy efficient intra-tile communication 节能瓦片内通信的拓扑探索

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357982

Jin Guo, A. Papanikolaou, F. Catthoor

引用次数: 3

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield 一种保证时钟偏差产生率的全局最小时钟分配网络增强算法

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357787

Bao Liu, A. Kahng, Xu Xu, Jiang Hu, G. Venkataraman

{"title":"A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield","authors":"Bao Liu, A. Kahng, Xu Xu, Jiang Hu, G. Venkataraman","doi":"10.1109/ASPDAC.2007.357787","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.357787","url":null,"abstract":"Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clock distribution network augmentation for guaranteed skew yield. We present theoretical analysis results on an inserted link in a clock network, which scales down local skew and skew variation, but may not guarantee global skew and skew variation reduction in general. We propose a global minimum clock network augmentation algorithm, which inserts links simultaneously between all nearest sink pairs, apply rule-based link removal, and perform link consolidation by Steiner minimum tree construction for wire-length reduction with guaranteed clock skew yield. Our experimental results show that our proposed algorithm achieves dominant clock network augmentation solutions, e.g., an average of 16% clock skew yield improvement, 9% maximum skew reduction, and 25% reduction of clock skew variation standard deviation with identical wirelength compared with previous best clock network link insertion methods (Venkataraman et al., 2005).","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128312850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique 利用动态可重构技术提高FPGA的执行速度

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357964

R. Pantonial, Md. Ashfaquzzaman Khan, N. Miyamoto, K. Kotani, S. Sugawa, T. Ohmi

引用次数: 4

Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware 低功耗实时VC-1/H的研制。264/MPEG-4视频处理硬件

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358058

M. Hase, Kazushi Akie, Masaki Nobori, Keisuke Matsumoto

引用次数: 18

A Retargetable Software Timing Analyzer Using Architecture Description Language 基于体系结构描述语言的可重目标软件时序分析仪

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358018

Xianfeng Li, Abhik Roychoudhury, T. Mitra, P. Mishra, Xu Cheng

引用次数: 13