2007 Asia and South Pacific Design Automation Conference最新文献_第10页

Meeting with the Forthcoming IC Design -- The Era of Power, Variability and NRE Explosion and a Bit of the Future -- 与即将到来的IC设计会面-功率，可变性和NRE爆炸的时代以及未来的一点-

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357773

T. Sakurai

引用次数: 2

Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC 基于SystemC的多处理器SoC设计灵活可执行的硬件/软件接口建模

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358017

P. Gerin, Hao Shen, A. Chureau, A. Bouchhima, A. Jerraya

引用次数: 28

An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools 兼容ARM7软件工具的嵌入式低功耗16位数据/指令微处理器

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358104

Fu-Ching Yang, Ing-Jer Huang

引用次数: 6

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning 基于吞吐量感知的微架构流水线优化

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358107

Yuchun Ma, Zhuoyuan Li, J. Cong, Xianlong Hong, Glenn D. Reinman, Sheqin Dong, Qiang Zhou

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引用次数: 12

DFM reality in sub-nanometer IC design 亚纳米集成电路设计中的DFM现实

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357990

N. Verghese, P. Hurat

引用次数: 4

Creating Explicit Communication in SoC Models Using Interactive Re-Coding 使用交互式重新编码在SoC模型中创建显式通信

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357791

Pramod Chandraiah, J. Peng, R. Dömer

引用次数: 15

Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method 基于切片逆回归(SIR)方法的参数约简变异性分析

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1049/iet-cds:20070185

A. Mitev, M. Marefat, D. Ma, Janet Roveda

{"title":"Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method","authors":"A. Mitev, M. Marefat, D. Ma, Janet Roveda","doi":"10.1049/iet-cds:20070185","DOIUrl":"https://doi.org/10.1049/iet-cds:20070185","url":null,"abstract":"With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a number of issues in the new generation IC design. One of the biggest challenges is the enormous number of process variation related parameters. These parameters represent numerous local and global variations, and pose a heavy burden in today's chip verification and design. This paper proposes a new way of reducing the statistical variations (which include both process parameters and design variables) according to their impacts on the overall circuit performance. The new approach creates an effective reduction subspace (ERS) and provides a transformation matrix by using the mean and variance of the response surface. With the generated transformation matrix, the proposed method maps the original statistical variations to a smaller set of variables with which we process variability analysis. Thus, the computational cost due to the number of variations is greatly reduced. Experimental results show that by using new method we can achieve 20% to 50% parameter reduction with only less than 8% error on average.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114072663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation 基于滤波器样条插值的低阶宽带互连模型实现

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358014

A. Nieuwoudt, Mehboob Alam, Y. Massoud

引用次数: 2

A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units 基于流水线阶段和功能单元规范的指令行为描述处理器生成方法

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358000

T. Shiro, Masaaki Abe, K. Sakanushi, Y. Takeuchi, M. Imai

引用次数: 3

Overview on Low Power SoC Design Technology 低功耗SoC设计技术综述

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358057

K. Usami

引用次数: 5