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2007 Asia and South Pacific Design Automation Conference最新文献

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Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation 硬件仿真中基于高效自动机的断言检查器综合
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358006
M. Boule, Z. Zilic
{"title":"Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation","authors":"M. Boule, Z. Zilic","doi":"10.1109/ASPDAC.2007.358006","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358006","url":null,"abstract":"In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used assertion-based verification (ABV) languages. A checker generator capable of transforming assertions into efficient circuits allows the adoption of ABV in hardware emulation. Towards that goal, we introduce the algorithms for sequence fusion and length matching intersection, two SERE operators that are not typically used over regular expressions. We also develop an algorithm for generating failure detection automata, a concept critical to extending regular expressions for ABV, as well as present our efficient symbol encoding. Experiments with complex sequences show that our tool outperforms the best known checker generator.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127613502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects 过渡偏斜编码:一种用于全局片上互连的功率和面积高效编码技术
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358068
Charbel J. Akl, M. Bayoumi
{"title":"Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects","authors":"Charbel J. Akl, M. Bayoumi","doi":"10.1109/ASPDAC.2007.358068","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358068","url":null,"abstract":"Global signaling is becoming more and more challenging as technology scales down toward the deep submicron. We propose a new bus encoding technique, transition skew coding, that targets many of the global interconnects challenges such as crosstalk, peak energy and current, switching and leakage power, repeaters area, wiring area, signal integrity and noise. Simulations are done on different bus lengths using a 90nm library. Repeaters sizing and spacing are optimized, and the proposed encoded bus is compared against a standard bus and a bus with shields inserted between every two wires. The encoding and decoding latencies are also analyzed. Simulations show that transition skew coding is efficient in terms of energy and area with low encoding and decoding latency overhead.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114169977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs fpga的高阶功率估计与低功耗设计空间探索
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358040
Deming Chen, J. Cong, Yiping Fan, Zhiru Zhang
{"title":"High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs","authors":"Deming Chen, J. Cong, Yiping Fan, Zhiru Zhang","doi":"10.1109/ASPDAC.2007.358040","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358040","url":null,"abstract":"In this paper, we present a simultaneous resource allocation and binding algorithm for FPGA power minimization. To fully validate our methodology and result, our work targets a real FPGA architecture - Altera Stratix FPGA, which includes generic logic elements, DSP cores, and memories, etc. We design a high-level power estimator for this architecture and evaluate its estimation accuracy against a commercial gate-level power estimator - Quartus II PowerPlay Analyzer. During the synthesis stage, we pay special attention to interconnections and multiplexers. We concentrate on resource allocation and binding tasks because they are the key steps to determine the interconnections. We use a novel approach to explore the design space. Experimental results show that our high-level power estimator is 8.7% away from PowerPlay Analyzer. Meanwhile, we are able to achieve a significant amount of power reduction (32%) with better circuit speed (16%) compared to a traditional resource allocation and binding algorithm.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131622623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
Runtime leakage power estimation technique for combinational circuits 组合电路运行时泄漏功率估计技术
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358062
Yu-Shiang Lin, D. Sylvester
{"title":"Runtime leakage power estimation technique for combinational circuits","authors":"Yu-Shiang Lin, D. Sylvester","doi":"10.1109/ASPDAC.2007.358062","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358062","url":null,"abstract":"This paper carefully examines subthreshold leakage during circuit operation (runtime) and develops a novel analysis technique to capture this important effect, which is currently ignored in traditional steady-state leakage calculation approaches. We implement novel dynamic and static estimation methods that provide significant speed improvements over full SPICE simulations and yield estimation errors of approximately 12% on average compared to more than 2times errors in steady-state based subthreshold leakage analysis.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123164574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
How Foundry can Help Improve your Bottom-Line? Accuracy Matters! 铸造厂如何帮助提高你的底线?精度很重要!
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357774
Fu-Chieh Hsu
{"title":"How Foundry can Help Improve your Bottom-Line? Accuracy Matters!","authors":"Fu-Chieh Hsu","doi":"10.1109/ASPDAC.2007.357774","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.357774","url":null,"abstract":"As the leading edge of technology advances into the nanometer era, process data accuracy becomes increasingly important to the success of product designs. The gap between theoretical benefit and benefit obtainable by designers grows wider with each new technology node. However, foundries and EDA tool vendors can collaborate to reclaim some of the lost benefits of these technology nodes. In this talk, I will discuss how foundries can contribute in the effort to reclaim lost benefits through better model and data accuracy, while EDA tool vendors contribute through improved design approaches. I will give some examples of TSMC's approaches in improving SPICE model accuracy and DFM accuracy, as well as collaboration with EDA tool vendors in creating our DFM Data Kit. By increasing awareness of TSMC's approach to this issue, I hope to stimulate discussion from all sides of the industry in the search for more solutions.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116037785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Architectural Optimizations for Text to Speech Synthesis in Embedded Systems 嵌入式系统中文本到语音合成的架构优化
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358002
Soumyajit Dey, M. Kedia, A. Basu
{"title":"Architectural Optimizations for Text to Speech Synthesis in Embedded Systems","authors":"Soumyajit Dey, M. Kedia, A. Basu","doi":"10.1109/ASPDAC.2007.358002","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358002","url":null,"abstract":"The increasing processing power of embedded devices have created the scope for certain applications that could previously be executed in desktop environments only, to migrate into handheld platforms. An important feature of the computing systems of modern times is their support for applications that interact with the user by synthesizing natural speech output. Such applications deliver state of the art performance in desktop environments. However, the real-time performance of such applications in handheld platforms with on-line incoming text streams have not been explored till date. In this work, the performance of a text to speech synthesis application is evaluated on embedded processor architectures and modifications in the underlying hardware platform are proposed for real time performance improvement of the concerned application.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121926095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Configurable Multi-Processor Platforms for Next Generation Embedded Systems 面向下一代嵌入式系统的可配置多处理器平台
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358076
D. Goodwin, C. Rowen, G. Martin
{"title":"Configurable Multi-Processor Platforms for Next Generation Embedded Systems","authors":"D. Goodwin, C. Rowen, G. Martin","doi":"10.1109/ASPDAC.2007.358076","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358076","url":null,"abstract":"Next-generation embedded systems in application domains such as multimedia, wired and wireless communications, and multipurpose portable devices, are increasingly turning to multiprocessor platforms as a vehicle for their realization. But entirely fixed platforms composed of entirely fixed components lack the flexibility and ability to be optimized to the application to offer the best solution in any of these areas. Configurability at multiple levels offers a much better chance to optimize the resulting multiprocessor platform. Existing and emerging technologies for configurable and extensible processors and the creation of configurable multiprocessor subsystem platforms offer significant capability to design teams to both differentiate and optimize their products.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115463235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications 一种新的可重构低功耗多媒体分布式算法体系结构
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358105
Zhenyu Liu, T. Arslan, A. Erdogan
{"title":"A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications","authors":"Zhenyu Liu, T. Arslan, A. Erdogan","doi":"10.1109/ASPDAC.2007.358105","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358105","url":null,"abstract":"The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low power consumption. Distributed arithmetic (DA) is a powerful algorithm widely used in many fields of multimedia for its efficiency. This paper presents a novel reconfigurable adder-based architecture for DA to realize the inner product which is the key computation in many digital signal processing applications. 1D DCT is mapped onto the architecture. Compared with some existing ASIC designs, the new architecture achieves good performance in area, speed and power.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128798525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors 用于防撞近程车载雷达传感器的22-29GHz超宽带CMOS脉冲发生器
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357957
Ahmet Öncü, B. W. Badalawa, Tong Wang, M. Fujishima
{"title":"22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors","authors":"Ahmet Öncü, B. W. Badalawa, Tong Wang, M. Fujishima","doi":"10.1109/ASPDAC.2007.357957","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.357957","url":null,"abstract":"The pseudo millimeter wave 22-29GHz ultra-wideband (UWB) is attractive for the applications in short-range (SR) automotive radar sensors in order to contribute to significant reduction of traffic fatalities. Although CMOS is suitable for the short-range radar since processing units can be implemented in the same chip with the UWB front-end building block, it is difficult to operate CMOS pulse generators at such a high frequency. To realize the pseudo-millimeter-wave band using CMOS, we have proposed a new pulse generator consisting of a series of delay cells and edge combiners with waveform shaping. As a result of measurement using 90nm CMOS technology, 1Gbps pulses are successfully generated with a power consumption of 1.4mW at a supply voltage of 0.9V. This result is the key technology for a one-chip SR cost effective radar sensors.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117189060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture 基于弹性流水线结构的H.264/AVC高清电视解码LSI的功耗和内存带宽降低
2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358001
K. Kawakami, Mitsuhiko Kuroda, H. Kawaguchi, M. Yoshimoto
{"title":"Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture","authors":"K. Kawakami, Mitsuhiko Kuroda, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ASPDAC.2007.358001","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358001","url":null,"abstract":"We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. The proposed pipeline can also reduce a required local bus bandwidth. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The proposed architecture reduces a power to 56% in a 90-nm process technology, compared to the conventional clock-gating scheme or a local bus bandwidth to 37.2%.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126264186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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