2007 Asia and South Pacific Design Automation Conference最新文献

Design Methodology for 2.4GHz Dual-Core Microprocessor 2.4GHz双核微处理器的设计方法

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358103

N. Ito, H. Komatsu, A. Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, H. Sugiyama, R. Yamashita, Ken-ichi Nabeya, H. Yoshino, H. Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda

引用次数: 1

Numerical Function Generators Using Edge-Valued Binary Decision Diagrams 使用边值二值决策图的数值函数生成器

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358041

Shinobu Nagayama, Tsutomu Sasao, J. T. Butler

引用次数: 6

Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion 金属填充插入引起的电容增加的简单而准确的模型

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358028

Youngmin Kim, D. Petranovic, D. Sylvester

{"title":"Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion","authors":"Youngmin Kim, D. Petranovic, D. Sylvester","doi":"10.1109/ASPDAC.2007.358028","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358028","url":null,"abstract":"Inserting metal fill to improve inter-level dielectric thickness planarity is an essential part of the modern design process. However, the inserted fill shapes impact the performance of signal interconnect by increasing capacitance. In this paper, we analyze and model the impact of the metal dummy on the signal capacitance with various parameters including their electrical characteristic, signal dimensions, and dummy shape and dimensions. Fill has differing impact on interconnects depending on whether the signal of interest is in the same layer as the fill or not. In particular intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has more impact on the ground capacitance component. Based on an analysis of fill impact on capacitance, we propose simple capacitance increment models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider the realistic case with both signals and metal fill in adjacent layers, we apply a weighting function approach in the ground capacitance model. We verify this model using simple test patterns and benchmark circuits and find that the models match well with field solver results (1.2% average error with much faster runtime than commercial extraction tools, the runtime overhead reduced by ~75% for all benchmark circuits).","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125774547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Retiming for Synchronous Data Flow Graphs 同步数据流程图的重新计时

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358032

N. Liveris, Chuan Lin, J. Wang, H. Zhou, P. Banerjee

引用次数: 10

Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection 通过时钟和操作吞吐量选择在行为综合中利用功率面积权衡

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358038

M. A. Ochoa-Montiel, B. Al-Hashimi, P. Kollig

引用次数: 8

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses 硬实时SoC总线的精确带宽控制仲裁算法

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357980

Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou

引用次数: 26

A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs 一种MTCMOS fpga中减少漏损的时序驱动算法

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358065

Hassan Hassan, M. Anis, M. Elmasry

引用次数: 5

Delay Uncertainty Reduction by Interconnect and Gate Splitting 通过互连和门分离降低延迟不确定性

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358067

Vineet Agarwal, J. Sun, A. Mitev, Janet Roveda

引用次数: 0

SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design SmartSmooth:一种用于数字凸数据的线性时间保持平滑算法，应用于VLSI设计

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.358045

Sanghamitra Roy, C. C. Chen

{"title":"SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design","authors":"Sanghamitra Roy, C. C. Chen","doi":"10.1109/ASPDAC.2007.358045","DOIUrl":"https://doi.org/10.1109/ASPDAC.2007.358045","url":null,"abstract":"Convex optimization problems are very popular in the VLSI design society due to their guaranteed convergence to a global optimal point. While optimizing tabular data, significant fitting efforts are required to fit the data into convex form. Fitting the tables into analytically convex forms like posynomials, suffers from excessive fitting errors, as the fitting problem may be non-convex. In recent literature optimal numerically convex tables have been proposed. Since these tables are numerical, it is extremely important to make the table data smooth, and yet preserve its convexity. The smoothness ensures that the convex optimizer behaves predictably and converges quickly to the global optimal point. The existing smoothing techniques either cannot preserve convexity, or require very high execution time. In this paper, we propose a linear time algorithm to smoothen a given numerically convex data and at the same time preserve convexity. Our proposed algorithm SmartSmooth can smoothen the data in linear time without introducing any additional error on the numerically convex data. We present our SmartSmooth results on industrial cell libraries. SmartSmooth when applied on convex tables produced by ConvexFit shows a 30times reduction in fitting square error over a posynomial fitting algorithm.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128546116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

LEAF: A System Level Leakage-Aware Floorplanner for SoCs 用于soc的系统级泄漏感知地板规划器

2007 Asia and South Pacific Design Automation Conference Pub Date : 2007-01-23 DOI: 10.1109/ASPDAC.2007.357998

Aseem Gupta, N. Dutt, F. Kurdahi, K. Khouri, M. Abadir

引用次数: 27