A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs

Abstract

A timing-driven MTCMOS (T-MTCMOS) CAD methodology is proposed for subthreshold leakage power reduction in nanometer FPGAs. The methodology uses the circuit timing information to tune the performance penalty due to sleep transistors according to the path delays, achieving an average leakage reduction of 44.36 % when applied to FPGA benchmarks using a CMOS 0.13mum process. Moreover, the methodology is applied to several FPGA architectures and CMOS technologies.